use of com.cburch.logisim.instance.Port in project logisim-evolution by reds-heig.
the class bin2bcd method updatePorts.
private void updatePorts(Instance instance) {
BitWidth nrofbits = instance.getAttributeValue(bin2bcd.ATTR_BinBits);
int NrOfPorts = (int) (Math.log10(1 << nrofbits.getWidth()) + 1.0);
Port[] ps = new Port[NrOfPorts + 1];
ps[BINin] = new Port((int) (-0.5 * InnerDistance), 0, Port.INPUT, bin2bcd.ATTR_BinBits);
ps[BINin].setToolTip(Strings.getter("BinairyInputTip"));
for (int i = NrOfPorts; i > 0; i--) {
ps[i] = new Port((NrOfPorts - i) * InnerDistance, -20, Port.OUTPUT, 4);
int value = (int) Math.pow(10.0, i - 1);
ps[i].setToolTip(Strings.getter(Integer.toString(value)));
}
instance.setPorts(ps);
}
use of com.cburch.logisim.instance.Port in project logisim-evolution by reds-heig.
the class SubcircuitFactory method computePorts.
void computePorts(Instance instance) {
Direction facing = instance.getAttributeValue(StdAttr.FACING);
Map<Location, Instance> portLocs = source.getAppearance().getPortOffsets(facing);
Port[] ports = new Port[portLocs.size()];
Instance[] pins = new Instance[portLocs.size()];
int i = -1;
for (Map.Entry<Location, Instance> portLoc : portLocs.entrySet()) {
i++;
Location loc = portLoc.getKey();
Instance pin = portLoc.getValue();
String type = Pin.FACTORY.isInputPin(pin) ? Port.INPUT : Port.OUTPUT;
BitWidth width = pin.getAttributeValue(StdAttr.WIDTH);
ports[i] = new Port(loc.getX(), loc.getY(), type, width);
pins[i] = pin;
String label = pin.getAttributeValue(StdAttr.LABEL);
if (label != null && label.length() > 0) {
ports[i].setToolTip(StringUtil.constantGetter(label));
}
}
CircuitAttributes attrs = (CircuitAttributes) instance.getAttributeSet();
attrs.setPinInstances(pins);
instance.setPorts(ports);
instance.recomputeBounds();
// since this affects the circuit's bounds
configureLabel(instance);
}
use of com.cburch.logisim.instance.Port in project logisim-evolution by reds-heig.
the class Buffer method configurePorts.
private void configurePorts(Instance instance) {
Direction facing = instance.getAttributeValue(StdAttr.FACING);
Port[] ports = new Port[2];
ports[0] = new Port(0, 0, Port.OUTPUT, StdAttr.WIDTH);
Location out = Location.create(0, 0).translate(facing, -20);
ports[1] = new Port(out.getX(), out.getY(), Port.INPUT, StdAttr.WIDTH);
instance.setPorts(ports);
}
use of com.cburch.logisim.instance.Port in project logisim-evolution by reds-heig.
the class VhdlHDLGeneratorFactory method GetPortMap.
@Override
public SortedMap<String, String> GetPortMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter, String HDLType) {
SortedMap<String, String> PortMap = new TreeMap<String, String>();
AttributeSet attrs = ComponentInfo.GetComponent().getAttributeSet();
VhdlContent content = attrs.getValue(VhdlEntity.CONTENT_ATTR);
Port[] inputs = content.getInputs();
Port[] outputs = content.getOutputs();
for (int i = 0; i < inputs.length; i++) PortMap.putAll(GetNetMap(inputs[i].getToolTip(), true, ComponentInfo, i, Reporter, HDLType, Nets));
for (int i = 0; i < outputs.length; i++) PortMap.putAll(GetNetMap(outputs[i].getToolTip(), true, ComponentInfo, i + inputs.length, Reporter, HDLType, Nets));
return PortMap;
}
use of com.cburch.logisim.instance.Port in project logisim-evolution by reds-heig.
the class VhdlEntity method propagate.
@Override
public /**
* Propagate signals through the VHDL component.
* Logisim doesn't have a VHDL simulation tool. So we need to use an external tool.
* We send signals to Questasim/Modelsim through a socket and a tcl binder. Then,
* a simulation step is done and the tcl server sends the output signals back to
* Logisim. Then we can set the VHDL component output properly.
*
* This can be done only if Logisim could connect to the tcl server (socket). This is
* done in Simulation.java.
*/
void propagate(InstanceState state) {
if (state.getProject().getVhdlSimulator().isEnabled() && state.getProject().getVhdlSimulator().isRunning()) {
VhdlSimulator vhdlSimulator = state.getProject().getVhdlSimulator();
for (Port p : state.getInstance().getPorts()) {
int index = state.getPortIndex(p);
Value val = state.getPortValue(index);
String vhdlEntityName = getHDLTopName(state.getAttributeSet());
String message = p.getType() + ":" + vhdlEntityName + "_" + p.getToolTip() + ":" + val.toBinaryString() + ":" + index;
vhdlSimulator.send(message);
}
vhdlSimulator.send("sync");
/* Get response from tcl server */
String server_response;
while ((server_response = vhdlSimulator.receive()) != null && server_response.length() > 0 && !server_response.equals("sync")) {
String[] parameters = server_response.split("\\:");
String busValue = parameters[1];
Value[] vector_values = new Value[busValue.length()];
int k = busValue.length() - 1;
for (char bit : busValue.toCharArray()) {
try {
switch(Character.getNumericValue(bit)) {
case 0:
vector_values[k] = Value.FALSE;
break;
case 1:
vector_values[k] = Value.TRUE;
break;
default:
vector_values[k] = Value.UNKNOWN;
break;
}
} catch (NumberFormatException e) {
vector_values[k] = Value.UNKNOWN;
}
k--;
}
state.setPort(Integer.parseInt(parameters[2]), Value.create(vector_values), 1);
}
/* VhdlSimulation stopped/disabled */
} else {
for (Port p : state.getInstance().getPorts()) {
int index = state.getPortIndex(p);
/* If it is an output */
if (p.getType() == 2) {
Value[] vector_values = new Value[p.getFixedBitWidth().getWidth()];
for (int k = 0; k < p.getFixedBitWidth().getWidth(); k++) {
vector_values[k] = Value.UNKNOWN;
}
state.setPort(index, Value.create(vector_values), 1);
}
}
new UnsupportedOperationException("VHDL component simulation is not supported. This could be because there is no Questasim/Modelsim simulation server running.");
}
}
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