Examples with ElementAttributes de.neemann.digital.core.element.ElementAttributes used on opensource projects

Example 76 with ElementAttributes

use of de.neemann.digital.core.element.ElementAttributes in project Digital by hneemann.

the class XOrTest method testXor.

public void testXor() throws Exception {
    ObservableValue a = new ObservableValue("a", 1);
    ObservableValue b = new ObservableValue("b", 1);
    Model model = new Model();
    XOr out = model.add(new XOr(new ElementAttributes().setBits(1)));
    out.setInputs(ovs(a, b));
    TestExecuter sc = new TestExecuter(model).setInputs(a, b).setOutputs(out.getOutputs());
    sc.check(0, 0, 0);
    sc.check(1, 0, 1);
    sc.check(0, 1, 1);
    sc.check(1, 1, 0);
}

Example 77 with ElementAttributes

use of de.neemann.digital.core.element.ElementAttributes in project Digital by hneemann.

the class ApplicationVHDLStdIOTest method testExtraction.

public void testExtraction() {
    ElementAttributes attr = extractParameters("LIBRARY ieee;\n" + "USE ieee.std_logic_1164.all;\n" + "USE ieee.std_logic_unsigned.all;\n" + "\n" + "entity add is\n" + "  port (\n" + "    a: in std_logic_vector(3 downto 0);\n" + "    b: in std_logic_vector(3 downto 0);\n" + "    c_i: in std_logic;\n" + "    s: out std_logic_vector(3 downto 0);\n" + "    c_o: out std_logic );\n" + "end add;\n" + "\n" + "architecture add_arch of add is\n" + "begin\n" + "end add_arch;", true);
    assertEquals("add", attr.getCleanLabel());
    assertEquals("a:4,b:4,c_i", attr.get(Keys.EXTERNAL_INPUTS));
    assertEquals("s:4,c_o", attr.get(Keys.EXTERNAL_OUTPUTS));
}

Example 78 with ElementAttributes

use of de.neemann.digital.core.element.ElementAttributes in project Digital by hneemann.

the class ApplicationVHDLStdIOTest method testExtractionUpper.

public void testExtractionUpper() {
    ElementAttributes attr = extractParameters("LIBRARY Ieee;\n" + "USE Ieee.std_logic_1164.all;\n" + "USE Ieee.std_logic_unsigned.all;\n" + "\n" + "Entity Add Is\n" + "  Port (\n" + "    A: In Std_logic_vector(3 Downto 0);\n" + "    B: In Std_logic_vector(3 Downto 0);\n" + "    C_i: In Std_logic;\n" + "    S: Out Std_logic_vector(3 Downto 0);\n" + "    C_o: Out Std_logic );\n" + "End Add;\n" + "\n" + "architecture Add_arch Of Add Is\n" + "begin\n" + "end Add_arch;", true);
    assertEquals("Add", attr.getCleanLabel());
    assertEquals("A:4,B:4,C_i", attr.get(Keys.EXTERNAL_INPUTS));
    assertEquals("S:4,C_o", attr.get(Keys.EXTERNAL_OUTPUTS));
}

Example 79 with ElementAttributes

use of de.neemann.digital.core.element.ElementAttributes in project Digital by hneemann.

the class ApplicationVHDLStdIOTest method testExtractionCompact.

public void testExtractionCompact() {
    ElementAttributes attr = extractParameters("library IEEE;\n" + "use IEEE.std_logic_1164.all;\n" + "use IEEE.numeric_std.all;\n" + "\n" + "\n" + "entity nBitZaehler is\n" + "\tport (LoadIn : in std_logic_vector (7 downto 0); load,reset,clk : in std_logic; CountOut : out std_logic_vector (7 downto 0));\n" + "end nBitZaehler;\n" + "\n" + "architecture nBitZaehlerRTL of nBitZaehler is\n" + "\tsignal ALUOut : unsigned(7 downto 0);  -- internal\n" + "\tsignal ALUIn : unsigned(7 downto 0);  -- internal\n" + "begin\n" + "end nBitZaehlerRTL;", true);
    assertEquals("nBitZaehler", attr.getCleanLabel());
    assertEquals("LoadIn:8,load,reset,clk", attr.get(Keys.EXTERNAL_INPUTS));
    assertEquals("CountOut:8", attr.get(Keys.EXTERNAL_OUTPUTS));
}

Example 80 with ElementAttributes

use of de.neemann.digital.core.element.ElementAttributes in project Digital by hneemann.

the class ApplicationVHDLStdIOTest method testExtractionComment.

public void testExtractionComment() {
    ElementAttributes attr = extractParameters("-- comment at start\n" + "library IEEE;\n" + "use IEEE.std_logic_1164.all;\n" + "use IEEE.numeric_std.all;\n" + "\n" + "\n" + "entity nBitZaehler is -- commnet\n" + "\tport (LoadIn : in std_logic_vector (7 downto 0);--comment \n" + "\tload,reset,clk : in std_logic; CountOut : out std_logic_vector (7 downto 0));--comment\n" + "end nBitZaehler;\n" + "\n" + "architecture nBitZaehlerRTL of nBitZaehler is\n" + "begin\n" + "end nBitZaehlerRTL;", true);
    assertEquals("nBitZaehler", attr.getCleanLabel());
    assertEquals("LoadIn:8,load,reset,clk", attr.get(Keys.EXTERNAL_INPUTS));
    assertEquals("CountOut:8", attr.get(Keys.EXTERNAL_OUTPUTS));
}