use of com.bfh.logisim.designrulecheck.Net in project logisim-evolution by reds-heig.
the class AbstractHDLGeneratorFactory method GetBusNameContinues.
public String GetBusNameContinues(NetlistComponent comp, int EndIndex, String HDLType, Netlist TheNets) {
String Result;
String BracketOpen = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? "(" : "[";
String BracketClose = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? ")" : "]";
String VectorLoopId = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? " DOWNTO " : ":";
if ((EndIndex < 0) || (EndIndex >= comp.NrOfEnds())) {
return "";
}
ConnectionEnd ConnectionInformation = comp.getEnd(EndIndex);
int NrOfBits = ConnectionInformation.NrOfBits();
if (NrOfBits == 1) {
return "";
}
if (!TheNets.IsContinuesBus(comp, EndIndex)) {
return "";
}
Net ConnectedNet = ConnectionInformation.GetConnection((byte) 0).GetParrentNet();
Result = BusName + Integer.toString(TheNets.GetNetId(ConnectedNet)) + BracketOpen + Integer.toString(ConnectionInformation.GetConnection((byte) (ConnectionInformation.NrOfBits() - 1)).GetParrentNetBitIndex()) + VectorLoopId + Integer.toString(ConnectionInformation.GetConnection((byte) (0)).GetParrentNetBitIndex()) + BracketClose;
return Result;
}
use of com.bfh.logisim.designrulecheck.Net in project logisim-evolution by reds-heig.
the class AbstractHDLGeneratorFactory method GetBusEntryName.
public String GetBusEntryName(NetlistComponent comp, int EndIndex, boolean FloatingNetTiedToGround, int bitindex, String HDLType, Netlist TheNets) {
StringBuffer Contents = new StringBuffer();
String BracketOpen = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? "(" : "[";
String BracketClose = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? ")" : "]";
if ((EndIndex >= 0) && (EndIndex < comp.NrOfEnds())) {
ConnectionEnd ThisEnd = comp.getEnd(EndIndex);
boolean IsOutput = ThisEnd.IsOutputEnd();
int NrOfBits = ThisEnd.NrOfBits();
if ((NrOfBits > 1) && (bitindex >= 0) && (bitindex < NrOfBits)) {
if (ThisEnd.GetConnection((byte) bitindex).GetParrentNet() == null) {
/* The net is not connected */
if (IsOutput) {
if (HDLType.equals(HDLGeneratorFactory.VHDL)) {
Contents.append("OPEN");
} else {
Contents.append("'bz");
}
} else {
Contents.append(GetZeroVector(ThisEnd.NrOfBits(), FloatingNetTiedToGround, HDLType));
}
} else {
Net ConnectedNet = ThisEnd.GetConnection((byte) bitindex).GetParrentNet();
int ConnectedNetBitIndex = ThisEnd.GetConnection((byte) bitindex).GetParrentNetBitIndex();
if (!ConnectedNet.isBus()) {
Contents.append(NetName + Integer.toString(TheNets.GetNetId(ConnectedNet)));
} else {
Contents.append(BusName + Integer.toString(TheNets.GetNetId(ConnectedNet)) + BracketOpen + Integer.toString(ConnectedNetBitIndex) + BracketClose);
}
}
}
}
return Contents.toString();
}
use of com.bfh.logisim.designrulecheck.Net in project logisim-evolution by reds-heig.
the class AbstractHDLGeneratorFactory method GetClockNetName.
public static String GetClockNetName(NetlistComponent comp, int EndIndex, Netlist TheNets) {
StringBuffer Contents = new StringBuffer();
if ((TheNets.GetCurrentHierarchyLevel() != null) && (EndIndex >= 0) && (EndIndex < comp.NrOfEnds())) {
ConnectionEnd EndData = comp.getEnd(EndIndex);
if (EndData.NrOfBits() == 1) {
Net ConnectedNet = EndData.GetConnection((byte) 0).GetParrentNet();
byte ConnectedNetBitIndex = EndData.GetConnection((byte) 0).GetParrentNetBitIndex();
/* Here we search for a clock net Match */
int clocksourceid = TheNets.GetClockSourceId(TheNets.GetCurrentHierarchyLevel(), ConnectedNet, ConnectedNetBitIndex);
if (clocksourceid >= 0) {
Contents.append(ClockTreeName + Integer.toString(clocksourceid));
}
}
}
return Contents.toString();
}
use of com.bfh.logisim.designrulecheck.Net in project logisim-evolution by reds-heig.
the class CircuitHDLGeneratorFactory method GetWireList.
@Override
public SortedMap<String, Integer> GetWireList(AttributeSet attrs, Netlist Nets) {
SortedMap<String, Integer> SignalMap = new TreeMap<String, Integer>();
/* First we define the nets */
for (Net ThisNet : Nets.GetAllNets()) {
if (!ThisNet.isBus() && ThisNet.IsRootNet()) {
SignalMap.put(NetName + Integer.toString(Nets.GetNetId(ThisNet)), 1);
}
}
/* now we define the busses */
for (Net ThisNet : Nets.GetAllNets()) {
if (ThisNet.isBus() && ThisNet.IsRootNet()) {
int NrOfBits = ThisNet.BitWidth();
SignalMap.put(BusName + Integer.toString(Nets.GetNetId(ThisNet)), NrOfBits);
}
}
return SignalMap;
}
use of com.bfh.logisim.designrulecheck.Net in project logisim-evolution by reds-heig.
the class CircuitHDLGeneratorFactory method GetHDLWiring.
public ArrayList<String> GetHDLWiring(String HDLType, Netlist TheNets) {
ArrayList<String> Contents = new ArrayList<String>();
StringBuffer OneLine = new StringBuffer();
String BracketOpen = (HDLType.equals(VHDL)) ? "(" : "[";
String BracketClose = (HDLType.equals(VHDL)) ? ")" : "]";
/* we cycle through all nets with a forcedrootnet annotation */
for (Net ThisNet : TheNets.GetAllNets()) {
if (ThisNet.IsForcedRootNet()) {
/* now we cycle through all the bits */
for (int bit = 0; bit < ThisNet.BitWidth(); bit++) {
/* First we perform all source connections */
for (ConnectionPoint Source : ThisNet.GetSourceNets(bit)) {
OneLine.setLength(0);
if (ThisNet.isBus()) {
OneLine.append(BusName + Integer.toString(TheNets.GetNetId(ThisNet)) + BracketOpen + bit + BracketClose);
} else {
OneLine.append(NetName + Integer.toString(TheNets.GetNetId(ThisNet)));
}
while (OneLine.length() < SallignmentSize) {
OneLine.append(" ");
}
if (HDLType.equals(VHDL)) {
String line = " " + OneLine.toString() + "<= " + BusName + Integer.toString(TheNets.GetNetId(Source.GetParrentNet())) + BracketOpen + Source.GetParrentNetBitIndex() + BracketClose + ";";
if (!Contents.contains(line))
Contents.add(line);
} else {
String line = " assign " + OneLine.toString() + "= " + BusName + Integer.toString(TheNets.GetNetId(Source.GetParrentNet())) + BracketOpen + Source.GetParrentNetBitIndex() + BracketClose + ";";
if (!Contents.contains(line))
Contents.add(line);
}
}
/* Next we perform all sink connections */
for (ConnectionPoint Source : ThisNet.GetSinkNets(bit)) {
OneLine.setLength(0);
OneLine.append(BusName + Integer.toString(TheNets.GetNetId(Source.GetParrentNet())) + BracketOpen + Source.GetParrentNetBitIndex() + BracketClose);
while (OneLine.length() < SallignmentSize) {
OneLine.append(" ");
}
if (HDLType.equals(VHDL)) {
OneLine.append("<= ");
} else {
OneLine.append("= ");
}
if (ThisNet.isBus()) {
OneLine.append(BusName + Integer.toString(TheNets.GetNetId(ThisNet)) + BracketOpen + bit + BracketClose);
} else {
OneLine.append(NetName + Integer.toString(TheNets.GetNetId(ThisNet)));
}
if (HDLType.equals(VHDL)) {
String line = " " + OneLine.toString() + ";";
if (!Contents.contains(line))
Contents.add(line);
} else {
String line = " assign " + OneLine.toString() + ";";
if (!Contents.contains(line))
Contents.add(line);
}
}
}
}
}
return Contents;
}
Aggregations