Examples with ClockIntegratorGeneric de.neemann.digital.hdl.model2.clock.ClockIntegratorGeneric used on opensource projects

Example 1 with ClockIntegratorGeneric

use of de.neemann.digital.hdl.model2.clock.ClockIntegratorGeneric in project Digital by hneemann.

the class HDLModelTest method testClock.

public void testClock() throws IOException, PinException, HDLException, NodeException, ElementNotFoundException {
    HDLCircuit hdl = getCircuit("dig/hdl/model2/clock.dig", new ClockIntegratorGeneric(10)).applyDefaultOptimizations();
    CodePrinterStr cp = new CodePrinterStr();
    hdl.print(cp);
    assertEquals("circuit main\n" + "  in(A:1 defines (A->1), C:1 defines (C->1))\n" + "  out(X:1 reads (X->1))\n" + "  sig(s0->1)\n" + "\n" + "  node simpleClockDivider\n" + "    in(cin:1 reads (C->1))\n" + "    out(cout:1 defines (s0->1))\n" + "  node D_FF\n" + "    in(D:1 reads (A->1), C:1 reads (s0->1))\n" + "    out(Q:1 defines (X->1), ~Q:1 is not used)\n" + "\n" + "end circuit main\n", cp.toString());
}

Example 2 with ClockIntegratorGeneric

use of de.neemann.digital.hdl.model2.clock.ClockIntegratorGeneric in project Digital by hneemann.

the class ClockTest method testGeneric.

public void testGeneric() throws PinException, NodeException, ElementNotFoundException, IOException, HDLException, HGSEvalException {
    String code = create(new ClockIntegratorGeneric(10));
    assertEquals("\n" + "LIBRARY ieee;\n" + "USE ieee.std_logic_1164.all;\n" + "USE ieee.numeric_std.all;\n" + "USE ieee.std_logic_unsigned.all;\n" + "\n" + "entity DIG_simpleClockDivider is\n" + "  generic (\n" + "    maxCounter : integer );  \n" + "  port (\n" + "    cout: out std_logic;\n" + "    cin: in std_logic );\n" + "end DIG_simpleClockDivider;\n" + "\n" + "architecture Behavioral of DIG_simpleClockDivider is\n" + "  -- Don't use a logic signal as clock source in a real world application!\n" + "  -- Use the on chip clock resources instead!\n" + "  signal counter: integer range 0 to maxCounter := 0;\n" + "  signal state: std_logic;\n" + "begin\n" + "  process (cin)\n" + "  begin\n" + "    if rising_edge(cin) then\n" + "       if counter = maxCounter then\n" + "          counter <= 0;\n" + "          state <= NOT (state);\n" + "       else\n" + "          counter <= counter+1;\n" + "       end if;\n" + "    end if;\n" + "  end process;\n" + "  cout <= state;\n" + "end Behavioral;\n" + "\n" + "\n" + "LIBRARY ieee;\n" + "USE ieee.std_logic_1164.all;\n" + "\n" + "entity DIG_D_FF is\n" + "  \n" + "  port ( D  : in std_logic;\n" + "         C  : in std_logic;\n" + "         Q  : out std_logic;\n" + "         notQ : out std_logic );\n" + "end DIG_D_FF;\n" + "\n" + "architecture Behavioral of DIG_D_FF is\n" + "   signal state : std_logic := '0';\n" + "begin\n" + "   Q    <= state;\n" + "   notQ <= NOT( state );\n" + "\n" + "   process(C)\n" + "   begin\n" + "      if rising_edge(C) then\n" + "        state  <= D;\n" + "      end if;\n" + "   end process;\n" + "end Behavioral;\n" + "\n" + "\n" + "LIBRARY ieee;\n" + "USE ieee.std_logic_1164.all;\n" + "USE ieee.numeric_std.all;\n" + "\n" + "entity main is\n" + "  port (\n" + "    A: in std_logic;\n" + "    C: in std_logic;\n" + "    X: out std_logic);\n" + "end main;\n" + "\n" + "architecture Behavioral of main is\n" + "  signal s0: std_logic;\n" + "begin\n" + "  gate0: entity work.DIG_simpleClockDivider\n" + "    generic map (\n" + "      maxCounter => 50)\n" + "    port map (\n" + "      cin => C,\n" + "      cout => s0);\n" + "  gate1: entity work.DIG_D_FF\n" + "    port map (\n" + "      D => A,\n" + "      C => s0,\n" + "      Q => X);\n" + "end Behavioral;\n", code);
}