Examples with AMD64Address org.graalvm.compiler.asm.amd64.AMD64Address used on opensource projects

Example 36 with AMD64Address

use of org.graalvm.compiler.asm.amd64.AMD64Address in project graal by oracle.

the class AMD64ArrayEqualsOp method emitAVXCompare.

private void emitAVXCompare(CompilationResultBuilder crb, AMD64MacroAssembler masm, Register result, Register array1, Register array2, Register length, Label trueLabel, Label falseLabel) {
    assert supportsAVX2(crb.target);
    Register vector1 = asRegister(vectorTemp1, AMD64Kind.DOUBLE);
    Register vector2 = asRegister(vectorTemp2, AMD64Kind.DOUBLE);
    Label loop = new Label();
    Label compareTail = new Label();
    boolean requiresNaNCheck = kind.isNumericFloat();
    Label loopCheck = new Label();
    Label nanCheck = new Label();
    // Compare 16-byte vectors
    // tail count (in bytes)
    masm.andl(result, AVX_VECTOR_SIZE - 1);
    // vector count (in bytes)
    masm.andl(length, ~(AVX_VECTOR_SIZE - 1));
    masm.jcc(ConditionFlag.Zero, compareTail);
    masm.leaq(array1, new AMD64Address(array1, length, Scale.Times1, 0));
    masm.leaq(array2, new AMD64Address(array2, length, Scale.Times1, 0));
    masm.negq(length);
    // Align the main loop
    masm.align(crb.target.wordSize * 2);
    masm.bind(loop);
    masm.vmovdqu(vector1, new AMD64Address(array1, length, Scale.Times1, 0));
    masm.vmovdqu(vector2, new AMD64Address(array2, length, Scale.Times1, 0));
    masm.vpxor(vector1, vector1, vector2);
    masm.vptest(vector1, vector1);
    masm.jcc(ConditionFlag.NotZero, requiresNaNCheck ? nanCheck : falseLabel);
    masm.bind(loopCheck);
    masm.addq(length, AVX_VECTOR_SIZE);
    masm.jcc(ConditionFlag.NotZero, loop);
    masm.testl(result, result);
    masm.jcc(ConditionFlag.Zero, trueLabel);
    if (requiresNaNCheck) {
        Label unalignedCheck = new Label();
        masm.jmpb(unalignedCheck);
        masm.bind(nanCheck);
        emitFloatCompareWithinRange(crb, masm, array1, array2, length, 0, falseLabel, AVX_VECTOR_SIZE);
        masm.jmpb(loopCheck);
        masm.bind(unalignedCheck);
    }
    /*
         * Compare the remaining bytes with an unaligned memory load aligned to the end of the
         * array.
         */
    masm.vmovdqu(vector1, new AMD64Address(array1, result, Scale.Times1, -AVX_VECTOR_SIZE));
    masm.vmovdqu(vector2, new AMD64Address(array2, result, Scale.Times1, -AVX_VECTOR_SIZE));
    masm.vpxor(vector1, vector1, vector2);
    masm.vptest(vector1, vector1);
    if (requiresNaNCheck) {
        masm.jcc(ConditionFlag.Zero, trueLabel);
        emitFloatCompareWithinRange(crb, masm, array1, array2, result, -AVX_VECTOR_SIZE, falseLabel, AVX_VECTOR_SIZE);
    } else {
        masm.jcc(ConditionFlag.NotZero, falseLabel);
    }
    masm.jmp(trueLabel);
    masm.bind(compareTail);
    masm.movl(length, result);
}

Example 37 with AMD64Address

use of org.graalvm.compiler.asm.amd64.AMD64Address in project graal by oracle.

the class AMD64DecrementingSafepointCheckOp method emitCode.

@Override
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
    assert SubstrateOptions.MultiThreaded.getValue();
    SubstrateRegisterConfig threadRegister = (SubstrateRegisterConfig) crb.codeCache.getRegisterConfig();
    masm.decrementl(new AMD64Address(threadRegister.getThreadRegister(), Math.toIntExact(Safepoint.getThreadLocalSafepointRequestedOffset())), 1);
}