Example 1 with SS
use of org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.SS in project graal by oracle.
the class AMD64Assembler method emitOperandHelper.
/**
* Emits the ModR/M byte and optionally the SIB byte for one memory operand and an opcode
* extension in the R field.
*
* @param force4Byte use 4 byte encoding for displacements that would normally fit in a byte
* @param additionalInstructionSize the number of bytes that will be emitted after the operand,
* so that the start position of the next instruction can be computed even though
* this instruction has not been completely emitted yet.
*/
protected void emitOperandHelper(int reg, AMD64Address addr, boolean force4Byte, int additionalInstructionSize) {
assert (reg & 0x07) == reg;
int regenc = reg << 3;
Register base = addr.getBase();
Register index = addr.getIndex();
AMD64Address.Scale scale = addr.getScale();
int disp = addr.getDisplacement();
if (base.equals(AMD64.rip)) {
// [00 000 101] disp32
assert index.equals(Register.None) : "cannot use RIP relative addressing with index register";
emitByte(0x05 | regenc);
if (codePatchingAnnotationConsumer != null && addr.instructionStartPosition >= 0) {
codePatchingAnnotationConsumer.accept(new AddressDisplacementAnnotation(addr.instructionStartPosition, position(), 4, position() + 4 + additionalInstructionSize));
}
emitInt(disp);
} else if (base.isValid()) {
int baseenc = base.isValid() ? encode(base) : 0;
if (index.isValid()) {
int indexenc = encode(index) << 3;
// [base + indexscale + disp]
if (disp == 0 && !base.equals(rbp) && !base.equals(r13)) {
// [00 reg 100][ss index base]
assert !index.equals(rsp) : "illegal addressing mode";
emitByte(0x04 | regenc);
emitByte(scale.log2 << 6 | indexenc | baseenc);
} else if (isByte(disp) && !force4Byte) {
// [01 reg 100][ss index base] imm8
assert !index.equals(rsp) : "illegal addressing mode";
emitByte(0x44 | regenc);
emitByte(scale.log2 << 6 | indexenc | baseenc);
emitByte(disp & 0xFF);
} else {
// [10 reg 100][ss index base] disp32
assert !index.equals(rsp) : "illegal addressing mode";
emitByte(0x84 | regenc);
emitByte(scale.log2 << 6 | indexenc | baseenc);
emitInt(disp);
}
} else if (base.equals(rsp) || base.equals(r12)) {
// [rsp + disp]
if (disp == 0) {
// [rsp]
// [00 reg 100][00 100 100]
emitByte(0x04 | regenc);
emitByte(0x24);
} else if (isByte(disp) && !force4Byte) {
// [rsp + imm8]
// [01 reg 100][00 100 100] disp8
emitByte(0x44 | regenc);
emitByte(0x24);
emitByte(disp & 0xFF);
} else {
// [rsp + imm32]
// [10 reg 100][00 100 100] disp32
emitByte(0x84 | regenc);
emitByte(0x24);
emitInt(disp);
}
} else {
// [base + disp]
assert !base.equals(rsp) && !base.equals(r12) : "illegal addressing mode";
if (disp == 0 && !base.equals(rbp) && !base.equals(r13)) {
// [base]
// [00 reg base]
emitByte(0x00 | regenc | baseenc);
} else if (isByte(disp) && !force4Byte) {
// [base + disp8]
// [01 reg base] disp8
emitByte(0x40 | regenc | baseenc);
emitByte(disp & 0xFF);
} else {
// [base + disp32]
// [10 reg base] disp32
emitByte(0x80 | regenc | baseenc);
emitInt(disp);
}
}
} else {
if (index.isValid()) {
int indexenc = encode(index) << 3;
// [00 reg 100][ss index 101] disp32
assert !index.equals(rsp) : "illegal addressing mode";
emitByte(0x04 | regenc);
emitByte(scale.log2 << 6 | indexenc | 0x05);
emitInt(disp);
} else {
// [disp] ABSOLUTE
// [00 reg 100][00 100 101] disp32
emitByte(0x04 | regenc);
emitByte(0x25);
emitInt(disp);
}
}
setCurAttributes(null);
}