Examples with ToplevelHDLGeneratorFactory com.bfh.logisim.hdlgenerator.ToplevelHDLGeneratorFactory used on opensource projects

Example 1 with ToplevelHDLGeneratorFactory

use of com.bfh.logisim.hdlgenerator.ToplevelHDLGeneratorFactory in project logisim-evolution by reds-heig.

the class FPGACommanderGui method writeHDL.

private boolean writeHDL() {
    String CircuitName = circuitsList.getSelectedItem().toString();
    if (!GenDirectory(AppPreferences.FPGA_Workspace.get() + File.separator + MyProject.getLogisimFile().getName())) {
        MyReporter.AddFatalError("Unable to create directory: \"" + AppPreferences.FPGA_Workspace.get() + File.separator + MyProject.getLogisimFile().getName() + "\"");
        return false;
    }
    String ProjectDir = AppPreferences.FPGA_Workspace.get() + File.separator + MyProject.getLogisimFile().getName();
    if (!ProjectDir.endsWith(File.separator)) {
        ProjectDir += File.separator;
    }
    LogisimFile myfile = MyProject.getLogisimFile();
    Circuit RootSheet = myfile.getCircuit(CircuitName);
    ProjectDir += CorrectLabel.getCorrectLabel(RootSheet.getName()) + File.separator;
    if (!CleanDirectory(ProjectDir)) {
        MyReporter.AddFatalError("Unable to cleanup old project files in directory: \"" + ProjectDir + "\"");
        return false;
    }
    if (!GenDirectory(ProjectDir)) {
        MyReporter.AddFatalError("Unable to create directory: \"" + ProjectDir + "\"");
        return false;
    }
    for (int i = 0; i < HDLPaths.length; i++) {
        if (!GenDirectory(ProjectDir + HDLPaths[i])) {
            MyReporter.AddFatalError("Unable to create directory: \"" + ProjectDir + HDLPaths[i] + "\"");
            return false;
        }
    }
    Set<String> GeneratedHDLComponents = new HashSet<String>();
    HDLGeneratorFactory Worker = RootSheet.getSubcircuitFactory().getHDLGenerator(AppPreferences.HDL_Type.get(), RootSheet.getStaticAttributes());
    if (Worker == null) {
        MyReporter.AddFatalError("Internal error on HDL generation, null pointer exception");
        return false;
    }
    if (!Worker.GenerateAllHDLDescriptions(GeneratedHDLComponents, ProjectDir, null, MyReporter, AppPreferences.HDL_Type.get())) {
        return false;
    }
    /* Here we generate the top-level shell */
    if (RootSheet.getNetList().NumberOfClockTrees() > 0) {
        TickComponentHDLGeneratorFactory Ticker = new TickComponentHDLGeneratorFactory(MyBoardInformation.fpga.getClockFrequency(), MenuSimulate.SupportedTickFrequencies[frequenciesList.getSelectedIndex()]);
        if (!AbstractHDLGeneratorFactory.WriteEntity(ProjectDir + Ticker.GetRelativeDirectory(AppPreferences.HDL_Type.get()), Ticker.GetEntity(RootSheet.getNetList(), null, Ticker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get()), Ticker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get())) {
            return false;
        }
        if (!AbstractHDLGeneratorFactory.WriteArchitecture(ProjectDir + Ticker.GetRelativeDirectory(AppPreferences.HDL_Type.get()), Ticker.GetArchitecture(RootSheet.getNetList(), null, Ticker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get()), Ticker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get())) {
            return false;
        }
        HDLGeneratorFactory ClockGen = RootSheet.getNetList().GetAllClockSources().get(0).getFactory().getHDLGenerator(AppPreferences.HDL_Type.get(), RootSheet.getNetList().GetAllClockSources().get(0).getAttributeSet());
        String CompName = RootSheet.getNetList().GetAllClockSources().get(0).getFactory().getHDLName(null);
        if (!AbstractHDLGeneratorFactory.WriteEntity(ProjectDir + ClockGen.GetRelativeDirectory(AppPreferences.HDL_Type.get()), ClockGen.GetEntity(RootSheet.getNetList(), null, CompName, MyReporter, AppPreferences.HDL_Type.get()), CompName, MyReporter, AppPreferences.HDL_Type.get())) {
            return false;
        }
        if (!AbstractHDLGeneratorFactory.WriteArchitecture(ProjectDir + ClockGen.GetRelativeDirectory(AppPreferences.HDL_Type.get()), ClockGen.GetArchitecture(RootSheet.getNetList(), null, CompName, MyReporter, AppPreferences.HDL_Type.get()), CompName, MyReporter, AppPreferences.HDL_Type.get())) {
            return false;
        }
    }
    Worker = new ToplevelHDLGeneratorFactory(MyBoardInformation.fpga.getClockFrequency(), MenuSimulate.SupportedTickFrequencies[frequenciesList.getSelectedIndex()], RootSheet, MyMappableResources);
    if (!AbstractHDLGeneratorFactory.WriteEntity(ProjectDir + Worker.GetRelativeDirectory(AppPreferences.HDL_Type.get()), Worker.GetEntity(RootSheet.getNetList(), null, ToplevelHDLGeneratorFactory.FPGAToplevelName, MyReporter, AppPreferences.HDL_Type.get()), Worker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get())) {
        return false;
    }
    if (!AbstractHDLGeneratorFactory.WriteArchitecture(ProjectDir + Worker.GetRelativeDirectory(AppPreferences.HDL_Type.get()), Worker.GetArchitecture(RootSheet.getNetList(), null, ToplevelHDLGeneratorFactory.FPGAToplevelName, MyReporter, AppPreferences.HDL_Type.get()), Worker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get())) {
        return false;
    }
    return true;
}