use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.
the class Netlist method GetGatedClockComponents.
public void GetGatedClockComponents(ArrayList<Netlist> HierarchyNetlists, NetlistComponent SubCircuit, Map<String, Map<NetlistComponent, Circuit>> NotGatedSet, Map<String, Map<NetlistComponent, Circuit>> GatedSet, Set<NetlistComponent> WarnedComponents, FPGAReport Reporter) {
/* First pass: we go down the tree */
for (NetlistComponent SubCirc : MySubCircuits) {
SubcircuitFactory sub = (SubcircuitFactory) SubCirc.GetComponent().getFactory();
ArrayList<String> NewHierarchyNames = new ArrayList<String>();
ArrayList<Netlist> NewHierarchyNetlists = new ArrayList<Netlist>();
NewHierarchyNames.addAll(GetCurrentHierarchyLevel());
NewHierarchyNames.add(CorrectLabel.getCorrectLabel(SubCirc.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)));
NewHierarchyNetlists.addAll(HierarchyNetlists);
NewHierarchyNetlists.add(sub.getSubcircuit().getNetList());
sub.getSubcircuit().getNetList().SetCurrentHierarchyLevel(NewHierarchyNames);
sub.getSubcircuit().getNetList().GetGatedClockComponents(NewHierarchyNetlists, SubCirc, NotGatedSet, GatedSet, WarnedComponents, Reporter);
}
/* Second pass: we find all components with a clock input and see if they are connected to a clock */
boolean GatedClock = false;
List<SourceInfo> PinSources = new ArrayList<SourceInfo>();
List<Set<Wire>> PinWires = new ArrayList<Set<Wire>>();
List<Set<NetlistComponent>> PinGatedComponents = new ArrayList<Set<NetlistComponent>>();
List<SourceInfo> NonPinSources = new ArrayList<SourceInfo>();
List<Set<Wire>> NonPinWires = new ArrayList<Set<Wire>>();
List<Set<NetlistComponent>> NonPinGatedComponents = new ArrayList<Set<NetlistComponent>>();
for (NetlistComponent comp : MyComponents) {
ComponentFactory fact = comp.GetComponent().getFactory();
if (fact instanceof DFlipFlop || fact instanceof JKFlipFlop || fact instanceof SRFlipFlop || fact instanceof TFlipFlop) {
AttributeSet attrs = comp.GetComponent().getAttributeSet();
if (IsFlipFlop(attrs)) {
GatedClock |= HasGatedClock(comp, comp.NrOfEnds() - 5, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
}
} else if (fact instanceof Counter) {
GatedClock |= HasGatedClock(comp, Counter.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
} else if (fact instanceof Ram) {
if (IsFlipFlop(comp.GetComponent().getAttributeSet()))
GatedClock |= HasGatedClock(comp, Ram.CLK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
} else if (fact instanceof Random) {
GatedClock |= HasGatedClock(comp, Random.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
} else if (fact instanceof Register) {
if (IsFlipFlop(comp.GetComponent().getAttributeSet()))
GatedClock |= HasGatedClock(comp, Register.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
} else if (fact instanceof ShiftRegister) {
GatedClock |= HasGatedClock(comp, ShiftRegister.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
}
}
/* We have two situations:
* 1) The gated clock net is generated locally, in this case we can mark them and add the current system to the non-gated set as
* each instance will be equal at higher/lower levels.
* 2) The gated clock nets are connected to a pin, in this case each instance of this circuit could be either gated or non-gated,
* we have to do something on the level higher and we mark this in the sets to be processed later.
*/
String MyName = CorrectLabel.getCorrectLabel(CircuitName);
if (HierarchyNetlists.size() > 1) {
if (GatedClock && PinSources.isEmpty()) {
GatedClock = false;
/* we have only non-pin driven gated clocks */
WarningForGatedClock(NonPinSources, NonPinGatedComponents, NonPinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_GatedClock"));
}
if (GatedClock && !PinSources.isEmpty()) {
for (int i = 0; i < PinSources.size(); i++) {
Reporter.AddSevereWarning(Strings.get("NetList_GatedClock"));
Reporter.AddWarningIncrement(Strings.get("NetList_TraceListBegin"));
SimpleDRCContainer warn = new SimpleDRCContainer(MyCircuit, Strings.get("NetList_GatedClockSink"), SimpleDRCContainer.LEVEL_NORMAL, SimpleDRCContainer.MARK_INSTANCE | SimpleDRCContainer.MARK_WIRE, true);
warn.AddMarkComponents(PinWires.get(i));
for (NetlistComponent comp : PinGatedComponents.get(i)) warn.AddMarkComponent(comp.GetComponent());
Reporter.AddWarning(warn);
WarningTraceForGatedClock(PinSources.get(i).getSource(), PinSources.get(i).getIndex(), HierarchyNetlists, CurrentHierarchyLevel, Reporter);
Reporter.AddWarningIncrement(Strings.get("NetList_TraceListEnd"));
}
}
/* we only mark if we are not at top-level */
if (GatedClock) {
if (GatedSet.containsKey(MyName))
GatedSet.get(MyName).put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
else {
Map<NetlistComponent, Circuit> newList = new HashMap<NetlistComponent, Circuit>();
newList.put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
GatedSet.put(MyName, newList);
}
} else {
if (NotGatedSet.containsKey(MyName))
NotGatedSet.get(MyName).put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
else {
Map<NetlistComponent, Circuit> newList = new HashMap<NetlistComponent, Circuit>();
newList.put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
NotGatedSet.put(MyName, newList);
}
}
} else {
/* At toplevel we warn for all possible gated clocks */
WarningForGatedClock(NonPinSources, NonPinGatedComponents, NonPinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_GatedClock"));
WarningForGatedClock(PinSources, PinGatedComponents, PinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_PossibleGatedClock"));
}
}
use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.
the class Netlist method circuitChanged.
@Override
public void circuitChanged(CircuitEvent event) {
int ev = event.getAction();
if (event.getData() instanceof InstanceComponent) {
InstanceComponent inst = (InstanceComponent) event.getData();
if (event.getCircuit().equals(MyCircuit)) {
switch(ev) {
case CircuitEvent.ACTION_ADD:
DRCStatus = DRC_REQUIRED;
if (inst.getFactory() instanceof SubcircuitFactory) {
SubcircuitFactory fac = (SubcircuitFactory) inst.getFactory();
Circuit sub = fac.getSubcircuit();
if (MySubCircuitMap.containsKey(sub)) {
MySubCircuitMap.put(sub, MySubCircuitMap.get(sub) + 1);
} else {
MySubCircuitMap.put(sub, 1);
sub.addCircuitListener(this);
}
}
break;
case CircuitEvent.ACTION_REMOVE:
DRCStatus = DRC_REQUIRED;
if (inst.getFactory() instanceof SubcircuitFactory) {
SubcircuitFactory fac = (SubcircuitFactory) inst.getFactory();
Circuit sub = fac.getSubcircuit();
if (MySubCircuitMap.containsKey(sub)) {
if (MySubCircuitMap.get(sub) == 1) {
MySubCircuitMap.remove(sub);
sub.removeCircuitListener(this);
} else {
MySubCircuitMap.put(sub, MySubCircuitMap.get(sub) - 1);
}
}
}
break;
case CircuitEvent.ACTION_CHANGE:
case CircuitEvent.ACTION_CLEAR:
case CircuitEvent.ACTION_INVALIDATE:
DRCStatus = DRC_REQUIRED;
break;
}
} else {
if (inst.getFactory() instanceof Pin) {
DRCStatus = DRC_REQUIRED;
}
}
}
}
use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.
the class Frame method setAttrTableModel.
void setAttrTableModel(AttrTableModel value) {
attrTable.setAttrTableModel(value);
if (value instanceof AttrTableToolModel) {
Tool tool = ((AttrTableToolModel) value).getTool();
toolbox.setHaloedTool(tool);
layoutToolbarModel.setHaloedTool(tool);
} else {
toolbox.setHaloedTool(null);
layoutToolbarModel.setHaloedTool(null);
}
if (value instanceof AttrTableComponentModel) {
Circuit circ = ((AttrTableComponentModel) value).getCircuit();
Component comp = ((AttrTableComponentModel) value).getComponent();
layoutCanvas.setHaloedComponent(circ, comp);
} else {
layoutCanvas.setHaloedComponent(null, null);
}
}
use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.
the class Frame method computeTitle.
private void computeTitle() {
String s;
Circuit circuit = proj.getCurrentCircuit();
String name = proj.getLogisimFile().getName();
if (circuit != null) {
s = StringUtil.format(Strings.get("titleCircFileKnown"), circuit.getName(), name);
} else {
s = StringUtil.format(Strings.get("titleFileKnown"), name);
}
this.setTitle(s + " (v " + Main.VERSION_NAME + ")");
myProjectListener.enableSave();
}
use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.
the class LayoutEditHandler method selectAll.
@Override
public void selectAll() {
Project proj = frame.getProject();
Selection sel = frame.getCanvas().getSelection();
selectSelectTool(proj);
Circuit circ = proj.getCurrentCircuit();
sel.addAll(circ.getWires());
sel.addAll(circ.getNonWires());
proj.repaintCanvas();
}
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