use of com.cburch.logisim.std.wiring.Pin in project logisim-evolution by reds-heig.
the class Netlist method HasGatedClock.
private boolean HasGatedClock(NetlistComponent comp, int ClockPinIndex, List<SourceInfo> PinSources, List<Set<Wire>> PinWires, List<Set<NetlistComponent>> PinGatedComponents, List<SourceInfo> NonPinSources, List<Set<Wire>> NonPinWires, List<Set<NetlistComponent>> NonPinGatedComponents, Set<NetlistComponent> WarnedComponents, FPGAReport Reporter) {
boolean GatedClock = false;
String ClockNetName = AbstractHDLGeneratorFactory.GetClockNetName(comp, ClockPinIndex, this);
if (ClockNetName.isEmpty()) {
/* we search for the source in case it is connected otherwise we ignore */
ConnectionPoint connection = comp.getEnd(ClockPinIndex).GetConnection((byte) 0);
Net connectedNet = connection.GetParrentNet();
byte connectedNetindex = connection.GetParrentNetBitIndex();
if (connectedNet != null) {
GatedClock = true;
if (connectedNet.IsForcedRootNet()) {
Set<Wire> Segments = new HashSet<Wire>();
Location loc = comp.GetComponent().getEnd(ClockPinIndex).getLocation();
for (Net thisOne : MyNets) if (thisOne.contains(loc)) {
if (!thisOne.IsRootNet())
Segments.addAll(thisOne.getWires());
}
SourceInfo SourceList = GetHiddenSource(connectedNet, connectedNetindex, MyComplexSplitters, null, new HashSet<String>(), Segments, Reporter);
ConnectionPoint source = SourceList.getSource();
if (source.GetComp().getFactory() instanceof Pin) {
int index = IndexOfEntry(PinSources, source, (int) connectedNetindex);
if (index < 0) {
PinSources.add(SourceList);
PinWires.add(Segments);
Set<NetlistComponent> comps = new HashSet<NetlistComponent>();
comps.add(comp);
comps.add(new NetlistComponent(source.GetComp()));
PinGatedComponents.add(comps);
} else {
PinGatedComponents.get(index).add(comp);
}
} else {
int index = IndexOfEntry(NonPinSources, source, (int) connectedNetindex);
if (index < 0) {
NonPinSources.add(SourceList);
NonPinWires.add(Segments);
Set<NetlistComponent> comps = new HashSet<NetlistComponent>();
comps.add(comp);
NonPinGatedComponents.add(comps);
} else {
NonPinGatedComponents.get(index).add(comp);
}
}
} else {
ArrayList<ConnectionPoint> SourceList = connectedNet.GetBitSources(connectedNetindex);
if (SourceList.size() != 1) {
Reporter.AddFatalError("BUG: Found multiple sources\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return GatedClock;
}
ConnectionPoint source = SourceList.get(0);
if (source.GetComp().getFactory() instanceof Pin) {
int index = IndexOfEntry(PinSources, source, (int) connectedNetindex);
if (index < 0) {
SourceInfo NewEntry = new SourceInfo(source, connectedNetindex);
PinSources.add(NewEntry);
PinWires.add(connectedNet.getWires());
Set<NetlistComponent> comps = new HashSet<NetlistComponent>();
comps.add(comp);
PinGatedComponents.add(comps);
} else {
PinGatedComponents.get(index).add(comp);
}
} else {
int index = IndexOfEntry(NonPinSources, source, (int) connectedNetindex);
if (index < 0) {
SourceInfo NewEntry = new SourceInfo(source, connectedNetindex);
NonPinSources.add(NewEntry);
NonPinWires.add(connectedNet.getWires());
Set<NetlistComponent> comps = new HashSet<NetlistComponent>();
comps.add(comp);
NonPinGatedComponents.add(comps);
} else {
NonPinGatedComponents.get(index).add(comp);
}
}
}
} else {
/* Add severe warning, we found a memory with an unconnected clock input */
if (!WarnedComponents.contains(comp)) {
SimpleDRCContainer warn = new SimpleDRCContainer(MyCircuit, Strings.get("NetList_NoClockConnection"), SimpleDRCContainer.LEVEL_SEVERE, SimpleDRCContainer.MARK_INSTANCE);
warn.AddMarkComponent(comp.GetComponent());
Reporter.AddWarning(warn);
WarnedComponents.add(comp);
}
}
}
return GatedClock;
}
use of com.cburch.logisim.std.wiring.Pin in project logisim-evolution by reds-heig.
the class Netlist method ProcessNormalComponent.
private boolean ProcessNormalComponent(Component comp, FPGAReport Reporter) {
NetlistComponent NormalComponent = new NetlistComponent(comp);
for (EndData ThisPin : comp.getEnds()) {
Net Connection = FindConnectedNet(ThisPin.getLocation());
if (Connection != null) {
int PinId = comp.getEnds().indexOf(ThisPin);
boolean PinIsSink = ThisPin.isInput();
ConnectionEnd ThisEnd = NormalComponent.getEnd(PinId);
Net RootNet = GetRootNet(Connection);
if (RootNet == null) {
Reporter.AddFatalError("BUG: Unable to find a root net for a normal component\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
for (byte bitid = 0; bitid < ThisPin.getWidth().getWidth(); bitid++) {
Byte RootNetBitIndex = GetRootNetIndex(Connection, bitid);
if (RootNetBitIndex < 0) {
Reporter.AddFatalError("BUG: Unable to find a root-net bit-index for a normal component\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
ConnectionPoint ThisSolderPoint = ThisEnd.GetConnection(bitid);
ThisSolderPoint.SetParrentNet(RootNet, RootNetBitIndex);
if (PinIsSink) {
RootNet.addSink(RootNetBitIndex, ThisSolderPoint);
} else {
RootNet.addSource(RootNetBitIndex, ThisSolderPoint);
}
}
}
}
if (comp.getFactory() instanceof Clock) {
MyClockGenerators.add(NormalComponent);
} else if (comp.getFactory() instanceof Pin) {
if (comp.getEnd(0).isInput()) {
MyOutputPorts.add(NormalComponent);
} else {
MyInputPorts.add(NormalComponent);
}
} else if (comp.getFactory() instanceof ReptarLocalBus) {
MyInOutPorts.add(NormalComponent);
MyInputPorts.add(NormalComponent);
MyOutputPorts.add(NormalComponent);
MyComponents.add(NormalComponent);
} else {
MyComponents.add(NormalComponent);
}
return true;
}
use of com.cburch.logisim.std.wiring.Pin in project logisim-evolution by reds-heig.
the class Netlist method circuitChanged.
@Override
public void circuitChanged(CircuitEvent event) {
int ev = event.getAction();
if (event.getData() instanceof InstanceComponent) {
InstanceComponent inst = (InstanceComponent) event.getData();
if (event.getCircuit().equals(MyCircuit)) {
switch(ev) {
case CircuitEvent.ACTION_ADD:
DRCStatus = DRC_REQUIRED;
if (inst.getFactory() instanceof SubcircuitFactory) {
SubcircuitFactory fac = (SubcircuitFactory) inst.getFactory();
Circuit sub = fac.getSubcircuit();
if (MySubCircuitMap.containsKey(sub)) {
MySubCircuitMap.put(sub, MySubCircuitMap.get(sub) + 1);
} else {
MySubCircuitMap.put(sub, 1);
sub.addCircuitListener(this);
}
}
break;
case CircuitEvent.ACTION_REMOVE:
DRCStatus = DRC_REQUIRED;
if (inst.getFactory() instanceof SubcircuitFactory) {
SubcircuitFactory fac = (SubcircuitFactory) inst.getFactory();
Circuit sub = fac.getSubcircuit();
if (MySubCircuitMap.containsKey(sub)) {
if (MySubCircuitMap.get(sub) == 1) {
MySubCircuitMap.remove(sub);
sub.removeCircuitListener(this);
} else {
MySubCircuitMap.put(sub, MySubCircuitMap.get(sub) - 1);
}
}
}
break;
case CircuitEvent.ACTION_CHANGE:
case CircuitEvent.ACTION_CLEAR:
case CircuitEvent.ACTION_INVALIDATE:
DRCStatus = DRC_REQUIRED;
break;
}
} else {
if (inst.getFactory() instanceof Pin) {
DRCStatus = DRC_REQUIRED;
}
}
}
}
use of com.cburch.logisim.std.wiring.Pin in project logisim-evolution by reds-heig.
the class CircuitState method processDirtyComponents.
void processDirtyComponents() {
if (!dirtyComponents.isEmpty()) {
// This seeming wasted copy is to avoid ConcurrentModifications
// if we used an iterator instead.
Object[] toProcess;
RuntimeException firstException = null;
for (int tries = 4; true; tries--) {
try {
toProcess = dirtyComponents.toArray();
break;
} catch (RuntimeException e) {
if (firstException == null)
firstException = e;
if (tries == 0) {
toProcess = new Object[0];
dirtyComponents = new CopyOnWriteArraySet<Component>();
throw firstException;
}
}
}
dirtyComponents.clear();
for (Object compObj : toProcess) {
if (compObj instanceof Component) {
Component comp = (Component) compObj;
comp.propagate(this);
if (comp.getFactory() instanceof Pin && parentState != null) {
// should be propagated in superstate
parentComp.propagate(parentState);
}
}
}
}
CircuitState[] subs = new CircuitState[substates.size()];
for (CircuitState substate : substates.toArray(subs)) {
substate.processDirtyComponents();
}
}
use of com.cburch.logisim.std.wiring.Pin in project logisim-evolution by reds-heig.
the class CircuitPins method transactionCompleted.
public void transactionCompleted(ReplacementMap repl) {
// determine the changes
Set<Instance> adds = new HashSet<Instance>();
Set<Instance> removes = new HashSet<Instance>();
Map<Instance, Instance> replaces = new HashMap<Instance, Instance>();
for (Component comp : repl.getAdditions()) {
if (comp.getFactory() instanceof Pin) {
Instance in = Instance.getInstanceFor(comp);
boolean added = pins.add(in);
if (added) {
comp.addComponentListener(myComponentListener);
in.getAttributeSet().addAttributeListener(myComponentListener);
adds.add(in);
}
}
}
for (Component comp : repl.getRemovals()) {
if (comp.getFactory() instanceof Pin) {
Instance in = Instance.getInstanceFor(comp);
boolean removed = pins.remove(in);
if (removed) {
comp.removeComponentListener(myComponentListener);
in.getAttributeSet().removeAttributeListener(myComponentListener);
Collection<Component> rs = repl.getComponentsReplacing(comp);
if (rs.isEmpty()) {
removes.add(in);
} else {
Component r = rs.iterator().next();
Instance rin = Instance.getInstanceFor(r);
adds.remove(rin);
replaces.put(in, rin);
}
}
}
}
appearanceManager.updatePorts(adds, removes, replaces, getPins());
}
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