use of com.cburch.logisim.std.io.PortIO in project logisim-evolution by reds-heig.
the class MappableResourcesContainer method IsMappable.
public boolean IsMappable(Map<String, ArrayList<Integer>> BoardComponents, FPGAReport MyReporter) {
for (ArrayList<String> key : myMappableResources.keySet()) {
NetlistComponent comp = myMappableResources.get(key);
/*
* we have a special case: a pinbus of the toplevel, this one has
* never a mainmaptype, so we should skip the test
*/
if (!((comp.GetComponent().getFactory() instanceof Pin) && (comp.GetComponent().getEnd(0).getWidth().getWidth() > 1))) {
/* for each component we first check the main map type */
String MainMapType = comp.GetIOInformationContainer().GetMainMapType().toString();
if (BoardComponents.containsKey(MainMapType)) {
/* okay it exists lets see if we have enough of those */
if (BoardComponents.get(MainMapType).size() > 0) {
if (comp.GetComponent().getFactory() instanceof PortIO || comp.GetComponent().getFactory() instanceof DipSwitch) {
/* Care of Port and Dip as their size may vary */
int NrOfBCRequired = comp.GetIOInformationContainer().GetNrOfInports() + comp.GetIOInformationContainer().GetNrOfOutports() + comp.GetIOInformationContainer().GetNrOfInOutports();
int bestComponentIdx = getBestComponent(BoardComponents.get(MainMapType), NrOfBCRequired);
if (bestComponentIdx > -1) {
BoardComponents.get(MainMapType).remove(bestComponentIdx);
continue;
}
} else {
/*
* no Problem, we have enough of those , we allocate
* and decrease
*/
BoardComponents.get(MainMapType).remove(BoardComponents.get(MainMapType).size() - 1);
continue;
}
}
} else {
/*
* The board does not have the main type, hence we have
* anyways to use alternate mapping
*/
comp.ToggleAlternateMapping(key);
comp.LockAlternateMapping(key);
}
}
/* Here we check if the component can be mapped to an alternate map */
int AltMapId = 0;
String AltMapType;
boolean found = false;
do {
AltMapType = comp.GetIOInformationContainer().GetAlternateMapType(AltMapId).toString();
if (!AltMapType.equals(IOComponentTypes.Unknown.toString())) {
if (BoardComponents.containsKey(AltMapType)) {
int NrOfBCRequired = comp.GetIOInformationContainer().GetNrOfInports() + comp.GetIOInformationContainer().GetNrOfOutports() + comp.GetIOInformationContainer().GetNrOfInOutports();
if (NrOfBCRequired <= BoardComponents.get(AltMapType).size()) {
// NrOfBCRequired);
for (int i = 0; i < NrOfBCRequired; i++) {
BoardComponents.get(AltMapType).remove(BoardComponents.get(AltMapType).size() - 1);
}
found = true;
break;
}
}
}
AltMapId++;
} while (!AltMapType.equals(IOComponentTypes.Unknown.toString()));
if (!found) {
if (comp.AlternateMappingEnabled(key)) {
comp.UnlockAlternateMapping(key);
comp.ToggleAlternateMapping(key);
}
MyReporter.AddError("The Target board " + currentBoardName + " does not have enough IO resources to map the design!");
MyReporter.AddError("The component \"" + MapNametoDisplayName(GetMapNamesList(key, comp).get(0)) + "\" cannot be placed!");
return false;
}
}
return true;
}
use of com.cburch.logisim.std.io.PortIO in project logisim-evolution by reds-heig.
the class CircuitHDLGeneratorFactory method GetPortMap.
@Override
public SortedMap<String, String> GetPortMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter, String HDLType) {
SortedMap<String, String> PortMap = new TreeMap<String, String>();
if (ComponentInfo != null) {
SubcircuitFactory sub = (SubcircuitFactory) ComponentInfo.GetComponent().getFactory();
Netlist MyNetList = sub.getSubcircuit().getNetList();
int NrOfClockTrees = MyNetList.NumberOfClockTrees();
int NrOfInputBubbles = MyNetList.NumberOfInputBubbles();
int NrOfOutputBubbles = MyNetList.NumberOfOutputBubbles();
int NrOfInputPorts = MyNetList.NumberOfInputPorts();
int NrOfInOutPorts = MyNetList.NumberOfInOutPorts();
int NrOfOutputPorts = MyNetList.NumberOfOutputPorts();
/* First we instantiate the Clock tree busses when present */
for (int i = 0; i < NrOfClockTrees; i++) {
PortMap.put(ClockTreeName + Integer.toString(i), ClockTreeName + Integer.toString(i));
}
if (MyNetList.RequiresGlobalClockConnection()) {
PortMap.put(TickComponentHDLGeneratorFactory.FPGAClock, TickComponentHDLGeneratorFactory.FPGAClock);
}
if (NrOfInputBubbles > 0) {
PortMap.put(HDLGeneratorFactory.LocalInputBubbleBusname, HDLGeneratorFactory.LocalInputBubbleBusname + GetBubbleIndex(ComponentInfo, HDLType, true));
}
if (NrOfOutputBubbles > 0) {
PortMap.put(HDLGeneratorFactory.LocalOutputBubbleBusname, HDLGeneratorFactory.LocalOutputBubbleBusname + GetBubbleIndex(ComponentInfo, HDLType, false));
}
if (NrOfInputPorts > 0) {
for (int i = 0; i < NrOfInputPorts; i++) {
NetlistComponent selected = MyNetList.GetInputPin(i);
if (selected != null) {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, false);
if (endid < 0) {
Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
} else {
PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
}
}
}
}
if (NrOfInOutPorts > 0) {
for (int i = 0; i < NrOfInOutPorts; i++) {
NetlistComponent selected = MyNetList.GetInOutPin(i);
if (selected != null) {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, false);
if (endid < 0) {
Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
} else {
PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
}
}
}
}
if (NrOfOutputPorts > 0) {
for (int i = 0; i < NrOfOutputPorts; i++) {
NetlistComponent selected = MyNetList.GetOutputPin(i);
if (selected != null) {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, true);
if (endid < 0) {
Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
} else {
PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
}
}
}
}
} else {
int NrOfClockTrees = Nets.NumberOfClockTrees();
int NrOfInputBubbles = Nets.NumberOfInputBubbles();
int NrOfOutputBubbles = Nets.NumberOfOutputBubbles();
int NrOfInputPorts = Nets.NumberOfInputPorts();
int NrOfInOutPorts = Nets.NumberOfInOutPorts();
int NrOfOutputPorts = Nets.NumberOfOutputPorts();
for (int i = 0; i < NrOfClockTrees; i++) {
PortMap.put(ClockTreeName + Integer.toString(i), "s_" + ClockTreeName + Integer.toString(i));
}
if (Nets.RequiresGlobalClockConnection()) {
PortMap.put(TickComponentHDLGeneratorFactory.FPGAClock, TickComponentHDLGeneratorFactory.FPGAClock);
}
if (NrOfInputBubbles > 0) {
PortMap.put(HDLGeneratorFactory.LocalInputBubbleBusname, "s_LOGISIM_INPUT_BUBBLES");
}
if (NrOfOutputBubbles > 0) {
PortMap.put(HDLGeneratorFactory.LocalOutputBubbleBusname, "s_LOGISIM_OUTPUT_BUBBLES");
}
if (NrOfInputPorts > 0) {
for (int i = 0; i < NrOfInputPorts; i++) {
NetlistComponent selected = Nets.GetInputPin(i);
if (selected != null) {
if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
MappableResourcesContainer mapInfo = ((ReptarLocalBus) selected.GetComponent().getFactory()).getMapInfo();
int start = mapInfo.GetFPGAInputPinId(mapInfo.currentBoardName + ":/" + selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
for (int j = 0; j < 13; j++) {
PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "_i(" + j + ")", FPGAInputPinName + "_" + (start + j));
}
} else {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
PortMap.put(PinLabel, "s_" + PinLabel);
}
}
}
}
if (NrOfInOutPorts > 0) {
for (int i = 0; i < NrOfInOutPorts; i++) {
NetlistComponent selected = Nets.GetInOutPin(i);
if (selected != null) {
if (selected.GetComponent().getFactory() instanceof PortIO) {
ArrayList<String> name = new ArrayList<String>();
MappableResourcesContainer mapInfo = ((PortIO) selected.GetComponent().getFactory()).getMapInfo();
int start = mapInfo.GetFPGAInOutPinId(mapInfo.currentBoardName + ":/" + selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int k = 0;
name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
for (int j = selected.GetGlobalBubbleId(name).GetInOutStartIndex(); j <= selected.GetGlobalBubbleId(name).GetInOutEndIndex(); j++) {
PortMap.put(LocalInOutBubbleBusname + "(" + j + ")", FPGAInOutPinName + "_" + (start + k));
k++;
}
} else if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
ArrayList<String> name = new ArrayList<String>();
name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
for (int j = selected.GetGlobalBubbleId(name).GetInOutStartIndex(); j <= selected.GetGlobalBubbleId(name).GetInOutEndIndex(); j++) {
PortMap.put(LocalInOutBubbleBusname + "(" + j + ")", FPGAInOutPinName + "_" + j);
}
} else {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
PortMap.put(PinLabel, "s_" + PinLabel);
}
}
}
}
if (NrOfOutputPorts > 0) {
for (int i = 0; i < NrOfOutputPorts; i++) {
NetlistComponent selected = Nets.GetOutputPin(i);
if (selected != null) {
if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
ArrayList<String> name = new ArrayList<String>();
name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int k = 0;
for (int j = selected.GetGlobalBubbleId(name).GetOutputStartIndex(); j <= selected.GetGlobalBubbleId(name).GetOutputEndIndex(); j++) {
PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "_o(" + k + ")", "FPGA_LB_OUT_" + k);
k++;
}
// for (int j =
// selected.GetGlobalBubbleId(name).GetOutputStartIndex();
// j <=
// selected.GetGlobalBubbleId(name).GetOutputEndIndex();
// j++) {
// PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)
// + "_o", FPGAOutputPinName + "_" + j);
// }
} else {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
PortMap.put(PinLabel, "s_" + PinLabel);
}
}
}
}
}
return PortMap;
}
use of com.cburch.logisim.std.io.PortIO in project logisim-evolution by reds-heig.
the class ToplevelHDLGeneratorFactory method GetModuleFunctionality.
@Override
public ArrayList<String> GetModuleFunctionality(Netlist TheNetlist, AttributeSet attrs, FPGAReport Reporter, String HDLType) {
ArrayList<String> Contents = new ArrayList<String>();
int NrOfClockTrees = TheNetlist.NumberOfClockTrees();
String Preamble = (HDLType.equals(VHDL)) ? "" : "assign ";
String BracketOpen = (HDLType.equals(VHDL)) ? "(" : "[";
String BracketClose = (HDLType.equals(VHDL)) ? ")" : "]";
String AssignOperator = (HDLType.equals(VHDL)) ? " <= " : " = ";
String NotOperator = (HDLType.equals(VHDL)) ? "NOT " : "~";
StringBuffer Temp = new StringBuffer();
/* First we process all pins */
Contents.addAll(MakeRemarkBlock("Here all signal adaptations are performed", 3, HDLType));
for (ArrayList<String> CompId : MyIOComponents.GetComponents()) {
if (MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof Pin) {
Component ThisPin = MyIOComponents.GetComponent(CompId).GetComponent();
ArrayList<String> MyMaps = MyIOComponents.GetMapNamesList(CompId);
if (MyMaps == null) {
Reporter.AddFatalError("Component has no map information, bizar! " + CompId.toString());
return Contents;
}
int PinPinId = 0;
for (int MapOffset = 0; MapOffset < MyMaps.size(); MapOffset++) {
String map = MyMaps.get(MapOffset);
int InputId = MyIOComponents.GetFPGAInputPinId(map);
int OutputId = MyIOComponents.GetFPGAOutputPinId(map);
int NrOfPins = MyIOComponents.GetNrOfPins(map);
boolean Invert = MyIOComponents.RequiresToplevelInversion(CompId, map);
for (int PinId = 0; PinId < NrOfPins; PinId++) {
Temp.setLength(0);
Temp.append(" " + Preamble);
if (InputId >= 0) {
Temp.append("s_" + CorrectLabel.getCorrectLabel(ThisPin.getAttributeSet().getValue(StdAttr.LABEL)));
if (ThisPin.getEnd(0).getWidth().getWidth() > 1) {
Temp.append(BracketOpen + PinPinId + BracketClose);
}
PinPinId++;
Temp.append(AssignOperator);
if (Invert) {
Temp.append(NotOperator);
}
Temp.append(HDLGeneratorFactory.FPGAInputPinName);
Temp.append("_" + Integer.toString(InputId + PinId));
Temp.append(";");
Contents.add(Temp.toString());
}
if (OutputId >= 0) {
Temp.append(HDLGeneratorFactory.FPGAOutputPinName);
Temp.append("_" + Integer.toString(OutputId + PinId));
Temp.append(AssignOperator);
if (Invert) {
Temp.append(NotOperator);
}
Temp.append("s_" + CorrectLabel.getCorrectLabel(ThisPin.getAttributeSet().getValue(StdAttr.LABEL)));
if (ThisPin.getEnd(0).getWidth().getWidth() > 1) {
Temp.append(BracketOpen + PinPinId + BracketClose);
}
PinPinId++;
Temp.append(";");
Contents.add(Temp.toString());
}
}
}
}
}
/* Now we process the bubbles */
Contents.addAll(MakeRemarkBlock("Here all inlined adaptations are performed", 3, HDLType));
for (ArrayList<String> CompId : MyIOComponents.GetComponents()) {
if (!(MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof Pin) && !(MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof PortIO) && !(MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof ReptarLocalBus)) {
HDLGeneratorFactory Generator = MyIOComponents.GetComponent(CompId).GetComponent().getFactory().getHDLGenerator(HDLType, MyIOComponents.GetComponent(CompId).GetComponent().getAttributeSet());
if (Generator == null) {
Reporter.AddError("No generator for component " + CompId.toString());
} else {
Contents.addAll(Generator.GetInlinedCode(HDLType, CompId, Reporter, MyIOComponents));
}
} else if (MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof ReptarLocalBus) {
((ReptarLocalBus) MyIOComponents.GetComponent(CompId).GetComponent().getFactory()).setMapInfo(MyIOComponents);
} else if (MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof PortIO) {
((PortIO) MyIOComponents.GetComponent(CompId).GetComponent().getFactory()).setMapInfo(MyIOComponents);
}
}
if (NrOfClockTrees > 0) {
Contents.addAll(MakeRemarkBlock("Here the clock tree components are defined", 3, HDLType));
TickComponentHDLGeneratorFactory Ticker = new TickComponentHDLGeneratorFactory(FpgaClockFrequency, TickFrequency);
Contents.addAll(Ticker.GetComponentMap(null, (long) 0, null, Reporter, "", HDLType));
long index = 0;
for (Component Clockgen : TheNetlist.GetAllClockSources()) {
NetlistComponent ThisClock = new NetlistComponent(Clockgen);
Contents.addAll(Clockgen.getFactory().getHDLGenerator(HDLType, ThisClock.GetComponent().getAttributeSet()).GetComponentMap(TheNetlist, index++, ThisClock, Reporter, "Bla", HDLType));
}
}
Contents.add("");
/* Here the map is performed */
Contents.addAll(MakeRemarkBlock("Here the toplevel component is connected", 3, HDLType));
CircuitHDLGeneratorFactory DUT = new CircuitHDLGeneratorFactory(MyCircuit);
Contents.addAll(DUT.GetComponentMap(TheNetlist, (long) 0, null, Reporter, CorrectLabel.getCorrectLabel(MyCircuit.getName()), HDLType));
return Contents;
}
Aggregations