use of com.bfh.logisim.fpgagui.MappableResourcesContainer in project logisim-evolution by reds-heig.
the class CircuitHDLGeneratorFactory method GetPortMap.
@Override
public SortedMap<String, String> GetPortMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter, String HDLType) {
SortedMap<String, String> PortMap = new TreeMap<String, String>();
if (ComponentInfo != null) {
SubcircuitFactory sub = (SubcircuitFactory) ComponentInfo.GetComponent().getFactory();
Netlist MyNetList = sub.getSubcircuit().getNetList();
int NrOfClockTrees = MyNetList.NumberOfClockTrees();
int NrOfInputBubbles = MyNetList.NumberOfInputBubbles();
int NrOfOutputBubbles = MyNetList.NumberOfOutputBubbles();
int NrOfInputPorts = MyNetList.NumberOfInputPorts();
int NrOfInOutPorts = MyNetList.NumberOfInOutPorts();
int NrOfOutputPorts = MyNetList.NumberOfOutputPorts();
/* First we instantiate the Clock tree busses when present */
for (int i = 0; i < NrOfClockTrees; i++) {
PortMap.put(ClockTreeName + Integer.toString(i), ClockTreeName + Integer.toString(i));
}
if (MyNetList.RequiresGlobalClockConnection()) {
PortMap.put(TickComponentHDLGeneratorFactory.FPGAClock, TickComponentHDLGeneratorFactory.FPGAClock);
}
if (NrOfInputBubbles > 0) {
PortMap.put(HDLGeneratorFactory.LocalInputBubbleBusname, HDLGeneratorFactory.LocalInputBubbleBusname + GetBubbleIndex(ComponentInfo, HDLType, true));
}
if (NrOfOutputBubbles > 0) {
PortMap.put(HDLGeneratorFactory.LocalOutputBubbleBusname, HDLGeneratorFactory.LocalOutputBubbleBusname + GetBubbleIndex(ComponentInfo, HDLType, false));
}
if (NrOfInputPorts > 0) {
for (int i = 0; i < NrOfInputPorts; i++) {
NetlistComponent selected = MyNetList.GetInputPin(i);
if (selected != null) {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, false);
if (endid < 0) {
Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
} else {
PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
}
}
}
}
if (NrOfInOutPorts > 0) {
for (int i = 0; i < NrOfInOutPorts; i++) {
NetlistComponent selected = MyNetList.GetInOutPin(i);
if (selected != null) {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, false);
if (endid < 0) {
Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
} else {
PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
}
}
}
}
if (NrOfOutputPorts > 0) {
for (int i = 0; i < NrOfOutputPorts; i++) {
NetlistComponent selected = MyNetList.GetOutputPin(i);
if (selected != null) {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, true);
if (endid < 0) {
Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
} else {
PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
}
}
}
}
} else {
int NrOfClockTrees = Nets.NumberOfClockTrees();
int NrOfInputBubbles = Nets.NumberOfInputBubbles();
int NrOfOutputBubbles = Nets.NumberOfOutputBubbles();
int NrOfInputPorts = Nets.NumberOfInputPorts();
int NrOfInOutPorts = Nets.NumberOfInOutPorts();
int NrOfOutputPorts = Nets.NumberOfOutputPorts();
for (int i = 0; i < NrOfClockTrees; i++) {
PortMap.put(ClockTreeName + Integer.toString(i), "s_" + ClockTreeName + Integer.toString(i));
}
if (Nets.RequiresGlobalClockConnection()) {
PortMap.put(TickComponentHDLGeneratorFactory.FPGAClock, TickComponentHDLGeneratorFactory.FPGAClock);
}
if (NrOfInputBubbles > 0) {
PortMap.put(HDLGeneratorFactory.LocalInputBubbleBusname, "s_LOGISIM_INPUT_BUBBLES");
}
if (NrOfOutputBubbles > 0) {
PortMap.put(HDLGeneratorFactory.LocalOutputBubbleBusname, "s_LOGISIM_OUTPUT_BUBBLES");
}
if (NrOfInputPorts > 0) {
for (int i = 0; i < NrOfInputPorts; i++) {
NetlistComponent selected = Nets.GetInputPin(i);
if (selected != null) {
if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
MappableResourcesContainer mapInfo = ((ReptarLocalBus) selected.GetComponent().getFactory()).getMapInfo();
int start = mapInfo.GetFPGAInputPinId(mapInfo.currentBoardName + ":/" + selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
for (int j = 0; j < 13; j++) {
PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "_i(" + j + ")", FPGAInputPinName + "_" + (start + j));
}
} else {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
PortMap.put(PinLabel, "s_" + PinLabel);
}
}
}
}
if (NrOfInOutPorts > 0) {
for (int i = 0; i < NrOfInOutPorts; i++) {
NetlistComponent selected = Nets.GetInOutPin(i);
if (selected != null) {
if (selected.GetComponent().getFactory() instanceof PortIO) {
ArrayList<String> name = new ArrayList<String>();
MappableResourcesContainer mapInfo = ((PortIO) selected.GetComponent().getFactory()).getMapInfo();
int start = mapInfo.GetFPGAInOutPinId(mapInfo.currentBoardName + ":/" + selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int k = 0;
name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
for (int j = selected.GetGlobalBubbleId(name).GetInOutStartIndex(); j <= selected.GetGlobalBubbleId(name).GetInOutEndIndex(); j++) {
PortMap.put(LocalInOutBubbleBusname + "(" + j + ")", FPGAInOutPinName + "_" + (start + k));
k++;
}
} else if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
ArrayList<String> name = new ArrayList<String>();
name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
for (int j = selected.GetGlobalBubbleId(name).GetInOutStartIndex(); j <= selected.GetGlobalBubbleId(name).GetInOutEndIndex(); j++) {
PortMap.put(LocalInOutBubbleBusname + "(" + j + ")", FPGAInOutPinName + "_" + j);
}
} else {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
PortMap.put(PinLabel, "s_" + PinLabel);
}
}
}
}
if (NrOfOutputPorts > 0) {
for (int i = 0; i < NrOfOutputPorts; i++) {
NetlistComponent selected = Nets.GetOutputPin(i);
if (selected != null) {
if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
ArrayList<String> name = new ArrayList<String>();
name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
int k = 0;
for (int j = selected.GetGlobalBubbleId(name).GetOutputStartIndex(); j <= selected.GetGlobalBubbleId(name).GetOutputEndIndex(); j++) {
PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "_o(" + k + ")", "FPGA_LB_OUT_" + k);
k++;
}
// for (int j =
// selected.GetGlobalBubbleId(name).GetOutputStartIndex();
// j <=
// selected.GetGlobalBubbleId(name).GetOutputEndIndex();
// j++) {
// PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)
// + "_o", FPGAOutputPinName + "_" + j);
// }
} else {
String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
PortMap.put(PinLabel, "s_" + PinLabel);
}
}
}
}
}
return PortMap;
}
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