Examples with Netlist com.bfh.logisim.designrulecheck.Netlist used on opensource projects

Example 1 with Netlist

use of com.bfh.logisim.designrulecheck.Netlist in project logisim-evolution by reds-heig.

the class FPGACommanderGui method MapDesign.

private boolean MapDesign() {
    String CircuitName = circuitsList.getSelectedItem().toString();
    LogisimFile myfile = MyProject.getLogisimFile();
    Circuit RootSheet = myfile.getCircuit(CircuitName);
    Netlist RootNetlist = RootSheet.getNetList();
    if (MyBoardInformation == null) {
        MyReporter.AddError("INTERNAL ERROR: No board information available ?!?");
        return false;
    }
    Map<String, ArrayList<Integer>> BoardComponents = MyBoardInformation.GetComponents();
    MyReporter.AddInfo("The Board " + MyBoardInformation.getBoardName() + " has:");
    for (String key : BoardComponents.keySet()) {
        MyReporter.AddInfo(BoardComponents.get(key).size() + " " + key + "(s)");
    }
    /*
		 * At this point I require 2 sorts of information: 1) A hierarchical
		 * netlist of all the wires that needs to be bubbled up to the toplevel
		 * in order to connect the LEDs, Buttons, etc. (hence for the HDL
		 * generation). 2) A list with all components that are required to be
		 * mapped to PCB components. Identification can be done by a hierarchy
		 * name plus component/sub-circuit name
		 */
    MyMappableResources = new MappableResourcesContainer(MyBoardInformation, RootNetlist);
    if (!MyMappableResources.IsMappable(BoardComponents, MyReporter)) {
        return false;
    }
    MapPannel.SetBoardInformation(MyBoardInformation);
    MapPannel.SetMappebleComponents(MyMappableResources);
    panel.setVisible(false);
    MapPannel.SetVisible(true);
    panel.setVisible(true);
    if (MyMappableResources.UnmappedList().isEmpty()) {
        MyMappableResources.BuildIOMappingInformation();
        return true;
    }
    MyReporter.AddError("Not all IO components have been mapped to the board " + MyBoardInformation.getBoardName() + " please map all components to continue!");
    return false;
}

Example 2 with Netlist

use of com.bfh.logisim.designrulecheck.Netlist in project logisim-evolution by reds-heig.

the class CircuitHDLGeneratorFactory method GenerateAllHDLDescriptions.

@Override
public boolean GenerateAllHDLDescriptions(Set<String> HandledComponents, String WorkingDir, ArrayList<String> Hierarchy, FPGAReport Reporter, String HDLType) {
    if (MyCircuit == null) {
        return false;
    }
    if (Hierarchy == null) {
        Hierarchy = new ArrayList<String>();
    }
    Netlist MyNetList = MyCircuit.getNetList();
    if (MyNetList == null) {
        return false;
    }
    String WorkPath = WorkingDir;
    if (!WorkPath.endsWith(File.separator)) {
        WorkPath += File.separator;
    }
    MyNetList.SetCurrentHierarchyLevel(Hierarchy);
    /* First we handle the normal components */
    for (NetlistComponent ThisComponent : MyNetList.GetNormalComponents()) {
        String ComponentName = ThisComponent.GetComponent().getFactory().getHDLName(ThisComponent.GetComponent().getAttributeSet());
        if (!HandledComponents.contains(ComponentName)) {
            HDLGeneratorFactory Worker = ThisComponent.GetComponent().getFactory().getHDLGenerator(HDLType, ThisComponent.GetComponent().getAttributeSet());
            if (Worker == null) {
                Reporter.AddFatalError("INTERNAL ERROR: Cannot find the VHDL generator factory for component " + ComponentName);
                return false;
            }
            if (!Worker.IsOnlyInlined(HDLType)) {
                if (!WriteEntity(WorkPath + Worker.GetRelativeDirectory(HDLType), Worker.GetEntity(MyNetList, ThisComponent.GetComponent().getAttributeSet(), ComponentName, Reporter, HDLType), ComponentName, Reporter, HDLType)) {
                    return false;
                }
                if (!WriteArchitecture(WorkPath + Worker.GetRelativeDirectory(HDLType), Worker.GetArchitecture(MyNetList, ThisComponent.GetComponent().getAttributeSet(), ComponentName, Reporter, HDLType), ComponentName, Reporter, HDLType)) {
                    return false;
                }
            }
            HandledComponents.add(ComponentName);
        }
    }
    /* Now we go down the hierarchy to get all other components */
    for (NetlistComponent ThisCircuit : MyNetList.GetSubCircuits()) {
        HDLGeneratorFactory Worker = ThisCircuit.GetComponent().getFactory().getHDLGenerator(HDLType, ThisCircuit.GetComponent().getAttributeSet());
        if (Worker == null) {
            Reporter.AddFatalError("INTERNAL ERROR: Unable to get a subcircuit VHDL generator for '" + ThisCircuit.GetComponent().getFactory().getName() + "'");
            return false;
        }
        Hierarchy.add(CorrectLabel.getCorrectLabel(ThisCircuit.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)));
        if (!Worker.GenerateAllHDLDescriptions(HandledComponents, WorkingDir, Hierarchy, Reporter, HDLType)) {
            return false;
        }
        Hierarchy.remove(Hierarchy.size() - 1);
    }
    /* I also have to generate myself */
    String ComponentName = CorrectLabel.getCorrectLabel(MyCircuit.getName());
    if (!HandledComponents.contains(ComponentName)) {
        if (!WriteEntity(WorkPath + GetRelativeDirectory(HDLType), GetEntity(MyNetList, null, ComponentName, Reporter, HDLType), ComponentName, Reporter, HDLType)) {
            return false;
        }
        // is the current circuit an 'empty vhdl box' ?
        String ArchName = MyCircuit.getStaticAttributes().getValue(CircuitAttributes.CIRCUIT_VHDL_PATH);
        if (!ArchName.isEmpty()) {
            if (!FileWriter.CopyArchitecture(ArchName, WorkPath + GetRelativeDirectory(HDLType), ComponentName, Reporter, HDLType)) {
                return false;
            }
        } else {
            if (!WriteArchitecture(WorkPath + GetRelativeDirectory(HDLType), GetArchitecture(MyNetList, null, ComponentName, Reporter, HDLType), ComponentName, Reporter, HDLType)) {
                return false;
            }
        }
        HandledComponents.add(ComponentName);
    }
    return true;
}

Example 3 with Netlist

use of com.bfh.logisim.designrulecheck.Netlist in project logisim-evolution by reds-heig.

the class CircuitHDLGeneratorFactory method GetPortMap.

@Override
public SortedMap<String, String> GetPortMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter, String HDLType) {
    SortedMap<String, String> PortMap = new TreeMap<String, String>();
    if (ComponentInfo != null) {
        SubcircuitFactory sub = (SubcircuitFactory) ComponentInfo.GetComponent().getFactory();
        Netlist MyNetList = sub.getSubcircuit().getNetList();
        int NrOfClockTrees = MyNetList.NumberOfClockTrees();
        int NrOfInputBubbles = MyNetList.NumberOfInputBubbles();
        int NrOfOutputBubbles = MyNetList.NumberOfOutputBubbles();
        int NrOfInputPorts = MyNetList.NumberOfInputPorts();
        int NrOfInOutPorts = MyNetList.NumberOfInOutPorts();
        int NrOfOutputPorts = MyNetList.NumberOfOutputPorts();
        /* First we instantiate the Clock tree busses when present */
        for (int i = 0; i < NrOfClockTrees; i++) {
            PortMap.put(ClockTreeName + Integer.toString(i), ClockTreeName + Integer.toString(i));
        }
        if (MyNetList.RequiresGlobalClockConnection()) {
            PortMap.put(TickComponentHDLGeneratorFactory.FPGAClock, TickComponentHDLGeneratorFactory.FPGAClock);
        }
        if (NrOfInputBubbles > 0) {
            PortMap.put(HDLGeneratorFactory.LocalInputBubbleBusname, HDLGeneratorFactory.LocalInputBubbleBusname + GetBubbleIndex(ComponentInfo, HDLType, true));
        }
        if (NrOfOutputBubbles > 0) {
            PortMap.put(HDLGeneratorFactory.LocalOutputBubbleBusname, HDLGeneratorFactory.LocalOutputBubbleBusname + GetBubbleIndex(ComponentInfo, HDLType, false));
        }
        if (NrOfInputPorts > 0) {
            for (int i = 0; i < NrOfInputPorts; i++) {
                NetlistComponent selected = MyNetList.GetInputPin(i);
                if (selected != null) {
                    String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                    int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, false);
                    if (endid < 0) {
                        Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
                    } else {
                        PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
                    }
                }
            }
        }
        if (NrOfInOutPorts > 0) {
            for (int i = 0; i < NrOfInOutPorts; i++) {
                NetlistComponent selected = MyNetList.GetInOutPin(i);
                if (selected != null) {
                    String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                    int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, false);
                    if (endid < 0) {
                        Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
                    } else {
                        PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
                    }
                }
            }
        }
        if (NrOfOutputPorts > 0) {
            for (int i = 0; i < NrOfOutputPorts; i++) {
                NetlistComponent selected = MyNetList.GetOutputPin(i);
                if (selected != null) {
                    String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                    int endid = Nets.GetEndIndex(ComponentInfo, PinLabel, true);
                    if (endid < 0) {
                        Reporter.AddFatalError("INTERNAL ERROR! Could not find the end-index of a sub-circuit component : '" + PinLabel + "'");
                    } else {
                        PortMap.putAll(GetNetMap(PinLabel, true, ComponentInfo, endid, Reporter, HDLType, Nets));
                    }
                }
            }
        }
    } else {
        int NrOfClockTrees = Nets.NumberOfClockTrees();
        int NrOfInputBubbles = Nets.NumberOfInputBubbles();
        int NrOfOutputBubbles = Nets.NumberOfOutputBubbles();
        int NrOfInputPorts = Nets.NumberOfInputPorts();
        int NrOfInOutPorts = Nets.NumberOfInOutPorts();
        int NrOfOutputPorts = Nets.NumberOfOutputPorts();
        for (int i = 0; i < NrOfClockTrees; i++) {
            PortMap.put(ClockTreeName + Integer.toString(i), "s_" + ClockTreeName + Integer.toString(i));
        }
        if (Nets.RequiresGlobalClockConnection()) {
            PortMap.put(TickComponentHDLGeneratorFactory.FPGAClock, TickComponentHDLGeneratorFactory.FPGAClock);
        }
        if (NrOfInputBubbles > 0) {
            PortMap.put(HDLGeneratorFactory.LocalInputBubbleBusname, "s_LOGISIM_INPUT_BUBBLES");
        }
        if (NrOfOutputBubbles > 0) {
            PortMap.put(HDLGeneratorFactory.LocalOutputBubbleBusname, "s_LOGISIM_OUTPUT_BUBBLES");
        }
        if (NrOfInputPorts > 0) {
            for (int i = 0; i < NrOfInputPorts; i++) {
                NetlistComponent selected = Nets.GetInputPin(i);
                if (selected != null) {
                    if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
                        MappableResourcesContainer mapInfo = ((ReptarLocalBus) selected.GetComponent().getFactory()).getMapInfo();
                        int start = mapInfo.GetFPGAInputPinId(mapInfo.currentBoardName + ":/" + selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                        for (int j = 0; j < 13; j++) {
                            PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "_i(" + j + ")", FPGAInputPinName + "_" + (start + j));
                        }
                    } else {
                        String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                        PortMap.put(PinLabel, "s_" + PinLabel);
                    }
                }
            }
        }
        if (NrOfInOutPorts > 0) {
            for (int i = 0; i < NrOfInOutPorts; i++) {
                NetlistComponent selected = Nets.GetInOutPin(i);
                if (selected != null) {
                    if (selected.GetComponent().getFactory() instanceof PortIO) {
                        ArrayList<String> name = new ArrayList<String>();
                        MappableResourcesContainer mapInfo = ((PortIO) selected.GetComponent().getFactory()).getMapInfo();
                        int start = mapInfo.GetFPGAInOutPinId(mapInfo.currentBoardName + ":/" + selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                        int k = 0;
                        name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                        for (int j = selected.GetGlobalBubbleId(name).GetInOutStartIndex(); j <= selected.GetGlobalBubbleId(name).GetInOutEndIndex(); j++) {
                            PortMap.put(LocalInOutBubbleBusname + "(" + j + ")", FPGAInOutPinName + "_" + (start + k));
                            k++;
                        }
                    } else if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
                        ArrayList<String> name = new ArrayList<String>();
                        name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                        for (int j = selected.GetGlobalBubbleId(name).GetInOutStartIndex(); j <= selected.GetGlobalBubbleId(name).GetInOutEndIndex(); j++) {
                            PortMap.put(LocalInOutBubbleBusname + "(" + j + ")", FPGAInOutPinName + "_" + j);
                        }
                    } else {
                        String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                        PortMap.put(PinLabel, "s_" + PinLabel);
                    }
                }
            }
        }
        if (NrOfOutputPorts > 0) {
            for (int i = 0; i < NrOfOutputPorts; i++) {
                NetlistComponent selected = Nets.GetOutputPin(i);
                if (selected != null) {
                    if (selected.GetComponent().getFactory() instanceof ReptarLocalBus) {
                        ArrayList<String> name = new ArrayList<String>();
                        name.add(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                        int k = 0;
                        for (int j = selected.GetGlobalBubbleId(name).GetOutputStartIndex(); j <= selected.GetGlobalBubbleId(name).GetOutputEndIndex(); j++) {
                            PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "_o(" + k + ")", "FPGA_LB_OUT_" + k);
                            k++;
                        }
                    // for (int j =
                    // selected.GetGlobalBubbleId(name).GetOutputStartIndex();
                    // j <=
                    // selected.GetGlobalBubbleId(name).GetOutputEndIndex();
                    // j++) {
                    // PortMap.put(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)
                    // + "_o", FPGAOutputPinName + "_" + j);
                    // }
                    } else {
                        String PinLabel = CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL));
                        PortMap.put(PinLabel, "s_" + PinLabel);
                    }
                }
            }
        }
    }
    return PortMap;
}