use of com.cburch.logisim.std.wiring.Clock in project logisim-evolution by reds-heig.
the class Netlist method ProcessNormalComponent.
private boolean ProcessNormalComponent(Component comp, FPGAReport Reporter) {
NetlistComponent NormalComponent = new NetlistComponent(comp);
for (EndData ThisPin : comp.getEnds()) {
Net Connection = FindConnectedNet(ThisPin.getLocation());
if (Connection != null) {
int PinId = comp.getEnds().indexOf(ThisPin);
boolean PinIsSink = ThisPin.isInput();
ConnectionEnd ThisEnd = NormalComponent.getEnd(PinId);
Net RootNet = GetRootNet(Connection);
if (RootNet == null) {
Reporter.AddFatalError("BUG: Unable to find a root net for a normal component\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
for (byte bitid = 0; bitid < ThisPin.getWidth().getWidth(); bitid++) {
Byte RootNetBitIndex = GetRootNetIndex(Connection, bitid);
if (RootNetBitIndex < 0) {
Reporter.AddFatalError("BUG: Unable to find a root-net bit-index for a normal component\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
ConnectionPoint ThisSolderPoint = ThisEnd.GetConnection(bitid);
ThisSolderPoint.SetParrentNet(RootNet, RootNetBitIndex);
if (PinIsSink) {
RootNet.addSink(RootNetBitIndex, ThisSolderPoint);
} else {
RootNet.addSource(RootNetBitIndex, ThisSolderPoint);
}
}
}
}
if (comp.getFactory() instanceof Clock) {
MyClockGenerators.add(NormalComponent);
} else if (comp.getFactory() instanceof Pin) {
if (comp.getEnd(0).isInput()) {
MyOutputPorts.add(NormalComponent);
} else {
MyInputPorts.add(NormalComponent);
}
} else if (comp.getFactory() instanceof ReptarLocalBus) {
MyInOutPorts.add(NormalComponent);
MyInputPorts.add(NormalComponent);
MyOutputPorts.add(NormalComponent);
MyComponents.add(NormalComponent);
} else {
MyComponents.add(NormalComponent);
}
return true;
}
use of com.cburch.logisim.std.wiring.Clock in project logisim-evolution by reds-heig.
the class Circuit method mutatorRemove.
void mutatorRemove(Component c) {
// logger.debug("mutatorRemove: {}", c);
locker.checkForWritePermission("remove");
Annotated = false;
MyNetList.clear();
if (c instanceof Wire) {
wires.remove(c);
} else {
wires.remove(c);
comps.remove(c);
ComponentFactory factory = c.getFactory();
if (factory instanceof Clock) {
clocks.remove(c);
} else if (factory instanceof SubcircuitFactory) {
SubcircuitFactory subcirc = (SubcircuitFactory) factory;
subcirc.getSubcircuit().circuitsUsingThis.remove(c);
}
c.removeComponentListener(myComponentListener);
}
fireEvent(CircuitEvent.ACTION_REMOVE, c);
}
use of com.cburch.logisim.std.wiring.Clock in project logisim-evolution by reds-heig.
the class Circuit method mutatorAdd.
void mutatorAdd(Component c) {
// logger.debug("mutatorAdd: {}", c);
locker.checkForWritePermission("add");
Annotated = false;
MyNetList.clear();
if (c instanceof Wire) {
Wire w = (Wire) c;
if (w.getEnd0().equals(w.getEnd1()))
return;
boolean added = wires.add(w);
if (!added)
return;
} else {
// add it into the circuit
boolean added = comps.add(c);
if (!added)
return;
wires.add(c);
ComponentFactory factory = c.getFactory();
if (factory instanceof Clock) {
clocks.add(c);
} else if (factory instanceof SubcircuitFactory) {
SubcircuitFactory subcirc = (SubcircuitFactory) factory;
subcirc.getSubcircuit().circuitsUsingThis.put(c, this);
}
c.addComponentListener(myComponentListener);
}
RemoveWrongLabels(c.getFactory().getName());
fireEvent(CircuitEvent.ACTION_ADD, c);
}
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