use of com.cburch.logisim.comp.EndData in project logisim-evolution by reds-heig.
the class Netlist method GetHiddenSinkNets.
private ArrayList<ConnectionPoint> GetHiddenSinkNets(Net thisNet, Byte bitIndex, ArrayList<Component> SplitterList, Component ActiveSplitter, Set<String> HandledNets, Boolean isSourceNet) {
ArrayList<ConnectionPoint> result = new ArrayList<ConnectionPoint>();
/*
* to prevent deadlock situations we check if we already looked at this
* net
*/
String NetId = Integer.toString(MyNets.indexOf(thisNet)) + "-" + Byte.toString(bitIndex);
if (HandledNets.contains(NetId)) {
return result;
} else {
HandledNets.add(NetId);
}
if (thisNet.hasBitSinks(bitIndex) && !isSourceNet) {
ConnectionPoint SolderPoint = new ConnectionPoint(null);
SolderPoint.SetParrentNet(thisNet, bitIndex);
result.add(SolderPoint);
}
/* Check if we have a connection to another splitter */
for (Component currentSplitter : SplitterList) {
if (ActiveSplitter != null) {
if (currentSplitter.equals(ActiveSplitter)) {
continue;
}
}
List<EndData> ends = currentSplitter.getEnds();
for (byte end = 0; end < ends.size(); end++) {
if (thisNet.contains(ends.get(end).getLocation())) {
/* Here we have to process the inherited bits of the parent */
byte[] BusBitConnection = ((Splitter) currentSplitter).GetEndpoints();
if (end == 0) {
/* this is a main net, find the connected end */
Byte SplitterEnd = BusBitConnection[bitIndex];
/* Find the corresponding Net index */
Byte Netindex = 0;
for (int index = 0; index < bitIndex; index++) {
if (BusBitConnection[index] == SplitterEnd) {
Netindex++;
}
}
/* Find the connected Net */
Net SlaveNet = null;
for (Net thisnet : MyNets) {
if (thisnet.contains(ends.get(SplitterEnd).getLocation())) {
SlaveNet = thisnet;
}
}
if (SlaveNet != null) {
if (SlaveNet.IsRootNet()) {
/* Trace down the slavenet */
result.addAll(GetHiddenSinkNets(SlaveNet, Netindex, SplitterList, currentSplitter, HandledNets, false));
} else {
result.addAll(GetHiddenSinkNets(SlaveNet.getParent(), SlaveNet.getBit(Netindex), SplitterList, currentSplitter, HandledNets, false));
}
}
} else {
ArrayList<Byte> Rootindices = new ArrayList<Byte>();
for (byte b = 0; b < BusBitConnection.length; b++) {
if (BusBitConnection[b] == end) {
Rootindices.add(b);
}
}
Net RootNet = null;
for (Net thisnet : MyNets) {
if (thisnet.contains(currentSplitter.getEnd(0).getLocation())) {
RootNet = thisnet;
}
}
if (RootNet != null) {
if (RootNet.IsRootNet()) {
result.addAll(GetHiddenSinkNets(RootNet, Rootindices.get(bitIndex), SplitterList, currentSplitter, HandledNets, false));
} else {
result.addAll(GetHiddenSinkNets(RootNet.getParent(), RootNet.getBit(Rootindices.get(bitIndex)), SplitterList, currentSplitter, HandledNets, false));
}
}
}
}
}
}
return result;
}
use of com.cburch.logisim.comp.EndData in project logisim-evolution by reds-heig.
the class Netlist method HasHiddenSource.
private boolean HasHiddenSource(Net thisNet, Byte bitIndex, List<Component> SplitterList, Component ActiveSplitter, Set<String> HandledNets) {
/*
* to prevent deadlock situations we check if we already looked at this
* net
*/
String NetId = Integer.toString(MyNets.indexOf(thisNet)) + "-" + Byte.toString(bitIndex);
if (HandledNets.contains(NetId)) {
return false;
} else {
HandledNets.add(NetId);
}
if (thisNet.hasBitSource(bitIndex)) {
return true;
}
/* Check if we have a connection to another splitter */
for (Component currentSplitter : SplitterList) {
if (currentSplitter.equals(ActiveSplitter)) {
continue;
}
List<EndData> ends = currentSplitter.getEnds();
for (byte end = 0; end < ends.size(); end++) {
if (thisNet.contains(ends.get(end).getLocation())) {
/* Here we have to process the inherited bits of the parent */
byte[] BusBitConnection = ((Splitter) currentSplitter).GetEndpoints();
if (end == 0) {
/* this is a main net, find the connected end */
Byte SplitterEnd = BusBitConnection[bitIndex];
/* Find the corresponding Net index */
Byte Netindex = 0;
for (int index = 0; index < bitIndex; index++) {
if (BusBitConnection[index] == SplitterEnd) {
Netindex++;
}
}
/* Find the connected Net */
Net SlaveNet = null;
for (Net thisnet : MyNets) {
if (thisnet.contains(ends.get(SplitterEnd).getLocation())) {
SlaveNet = thisnet;
}
}
if (SlaveNet != null) {
if (SlaveNet.IsRootNet()) {
/* Trace down the slavenet */
if (HasHiddenSource(SlaveNet, Netindex, SplitterList, currentSplitter, HandledNets)) {
return true;
}
} else {
if (HasHiddenSource(SlaveNet.getParent(), SlaveNet.getBit(Netindex), SplitterList, currentSplitter, HandledNets)) {
return true;
}
}
}
} else {
ArrayList<Byte> Rootindices = new ArrayList<Byte>();
for (byte b = 0; b < BusBitConnection.length; b++) {
if (BusBitConnection[b] == end) {
Rootindices.add(b);
}
}
Net RootNet = null;
for (Net thisnet : MyNets) {
if (thisnet.contains(currentSplitter.getEnd(0).getLocation())) {
RootNet = thisnet;
}
}
if (RootNet != null) {
if (RootNet.IsRootNet()) {
if (HasHiddenSource(RootNet, Rootindices.get(bitIndex), SplitterList, currentSplitter, HandledNets)) {
return true;
}
} else {
if (HasHiddenSource(RootNet.getParent(), RootNet.getBit(Rootindices.get(bitIndex)), SplitterList, currentSplitter, HandledNets)) {
return true;
}
}
}
}
}
}
}
return false;
}
use of com.cburch.logisim.comp.EndData in project logisim-evolution by reds-heig.
the class Netlist method ProcessSubcircuit.
private boolean ProcessSubcircuit(Component comp, FPGAReport Reporter) {
NetlistComponent Subcircuit = new NetlistComponent(comp);
SubcircuitFactory sub = (SubcircuitFactory) comp.getFactory();
Instance[] subPins = ((CircuitAttributes) comp.getAttributeSet()).getPinInstances();
Netlist subNetlist = sub.getSubcircuit().getNetList();
for (EndData ThisPin : comp.getEnds()) {
Net Connection = FindConnectedNet(ThisPin.getLocation());
int PinId = comp.getEnds().indexOf(ThisPin);
int SubPortIndex = subNetlist.GetPortInfo(subPins[PinId].getAttributeValue(StdAttr.LABEL));
if (SubPortIndex < 0) {
Reporter.AddFatalError("BUG: Unable to find pin in sub-circuit\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
if (Connection != null) {
boolean PinIsSink = ThisPin.isInput();
Net RootNet = GetRootNet(Connection);
if (RootNet == null) {
Reporter.AddFatalError("BUG: Unable to find a root net for sub-circuit\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
for (byte bitid = 0; bitid < ThisPin.getWidth().getWidth(); bitid++) {
Byte RootNetBitIndex = GetRootNetIndex(Connection, bitid);
if (RootNetBitIndex < 0) {
Reporter.AddFatalError("BUG: Unable to find a root-net bit-index for sub-circuit\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
Subcircuit.getEnd(PinId).GetConnection(bitid).SetParrentNet(RootNet, RootNetBitIndex);
if (PinIsSink) {
RootNet.addSink(RootNetBitIndex, Subcircuit.getEnd(PinId).GetConnection(bitid));
} else {
RootNet.addSource(RootNetBitIndex, Subcircuit.getEnd(PinId).GetConnection(bitid));
}
/*
* Special handling for sub-circuits; we have to find out
* the connection to the corresponding net in the underlying
* net-list; At this point the underlying net-lists have
* already been generated.
*/
Subcircuit.getEnd(PinId).GetConnection(bitid).setChildsPortIndex(SubPortIndex);
}
} else {
for (byte bitid = 0; bitid < ThisPin.getWidth().getWidth(); bitid++) {
Subcircuit.getEnd(PinId).GetConnection(bitid).setChildsPortIndex(SubPortIndex);
}
}
}
MySubCircuits.add(Subcircuit);
return true;
}
use of com.cburch.logisim.comp.EndData in project logisim-evolution by reds-heig.
the class Netlist method ProcessNormalComponent.
private boolean ProcessNormalComponent(Component comp, FPGAReport Reporter) {
NetlistComponent NormalComponent = new NetlistComponent(comp);
for (EndData ThisPin : comp.getEnds()) {
Net Connection = FindConnectedNet(ThisPin.getLocation());
if (Connection != null) {
int PinId = comp.getEnds().indexOf(ThisPin);
boolean PinIsSink = ThisPin.isInput();
ConnectionEnd ThisEnd = NormalComponent.getEnd(PinId);
Net RootNet = GetRootNet(Connection);
if (RootNet == null) {
Reporter.AddFatalError("BUG: Unable to find a root net for a normal component\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
for (byte bitid = 0; bitid < ThisPin.getWidth().getWidth(); bitid++) {
Byte RootNetBitIndex = GetRootNetIndex(Connection, bitid);
if (RootNetBitIndex < 0) {
Reporter.AddFatalError("BUG: Unable to find a root-net bit-index for a normal component\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return false;
}
ConnectionPoint ThisSolderPoint = ThisEnd.GetConnection(bitid);
ThisSolderPoint.SetParrentNet(RootNet, RootNetBitIndex);
if (PinIsSink) {
RootNet.addSink(RootNetBitIndex, ThisSolderPoint);
} else {
RootNet.addSource(RootNetBitIndex, ThisSolderPoint);
}
}
}
}
if (comp.getFactory() instanceof Clock) {
MyClockGenerators.add(NormalComponent);
} else if (comp.getFactory() instanceof Pin) {
if (comp.getEnd(0).isInput()) {
MyOutputPorts.add(NormalComponent);
} else {
MyInputPorts.add(NormalComponent);
}
} else if (comp.getFactory() instanceof ReptarLocalBus) {
MyInOutPorts.add(NormalComponent);
MyInputPorts.add(NormalComponent);
MyOutputPorts.add(NormalComponent);
MyComponents.add(NormalComponent);
} else {
MyComponents.add(NormalComponent);
}
return true;
}
use of com.cburch.logisim.comp.EndData in project logisim-evolution by reds-heig.
the class CircuitWires method computeBundleMap.
// To be called by getBundleMap only
private void computeBundleMap(BundleMap ret) {
// create bundles corresponding to wires and tunnels
connectWires(ret);
connectTunnels(ret);
connectPullResistors(ret);
// merge any WireBundle objects united by previous steps
for (Iterator<WireBundle> it = ret.getBundles().iterator(); it.hasNext(); ) {
WireBundle b = it.next();
WireBundle bpar = b.find();
if (bpar != b) {
// b isn't group's representative
for (Location pt : b.points) {
ret.setBundleAt(pt, bpar);
bpar.points.add(pt);
}
bpar.addPullValue(b.getPullValue());
it.remove();
}
}
// make a WireBundle object for each end of a splitter
for (Splitter spl : splitters) {
List<EndData> ends = new ArrayList<EndData>(spl.getEnds());
for (EndData end : ends) {
Location p = end.getLocation();
WireBundle pb = ret.createBundleAt(p);
pb.setWidth(end.getWidth(), p);
}
}
// based on components
for (Location p : ret.getBundlePoints()) {
WireBundle pb = ret.getBundleAt(p);
BitWidth width = points.getWidth(p);
if (width != BitWidth.UNKNOWN) {
pb.setWidth(width, p);
}
}
// determine the bundles at the end of each splitter
for (Splitter spl : splitters) {
List<EndData> ends = new ArrayList<EndData>(spl.getEnds());
int index = -1;
for (EndData end : ends) {
index++;
Location p = end.getLocation();
WireBundle pb = ret.getBundleAt(p);
if (pb != null) {
pb.setWidth(end.getWidth(), p);
spl.wire_data.end_bundle[index] = pb;
}
}
}
// unite threads going through splitters
for (Splitter spl : splitters) {
synchronized (spl) {
SplitterAttributes spl_attrs = (SplitterAttributes) spl.getAttributeSet();
byte[] bit_end = spl_attrs.bit_end;
SplitterData spl_data = spl.wire_data;
WireBundle from_bundle = spl_data.end_bundle[0];
if (from_bundle == null || !from_bundle.isValid())
continue;
for (int i = 0; i < bit_end.length; i++) {
int j = bit_end[i];
if (j > 0) {
int thr = spl.bit_thread[i];
WireBundle to_bundle = spl_data.end_bundle[j];
WireThread[] to_threads = to_bundle.threads;
if (to_threads != null && to_bundle.isValid()) {
WireThread[] from_threads = from_bundle.threads;
if (i >= from_threads.length) {
throw new ArrayIndexOutOfBoundsException("from " + i + " of " + from_threads.length);
}
if (thr >= to_threads.length) {
throw new ArrayIndexOutOfBoundsException("to " + thr + " of " + to_threads.length);
}
from_threads[i].unite(to_threads[thr]);
}
}
}
}
}
// merge any threads united by previous step
for (WireBundle b : ret.getBundles()) {
if (b.isValid() && b.threads != null) {
for (int i = 0; i < b.threads.length; i++) {
WireThread thr = b.threads[i].find();
b.threads[i] = thr;
thr.getBundles().add(new ThreadBundle(i, b));
}
}
}
// All threads are sewn together! Compute the exception set before
// leaving
Collection<WidthIncompatibilityData> exceptions = points.getWidthIncompatibilityData();
if (exceptions != null && exceptions.size() > 0) {
for (WidthIncompatibilityData wid : exceptions) {
ret.addWidthIncompatibilityData(wid);
}
}
for (WireBundle b : ret.getBundles()) {
WidthIncompatibilityData e = b.getWidthIncompatibilityData();
if (e != null)
ret.addWidthIncompatibilityData(e);
}
}
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