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Example 1 with CircuitAttributes

use of com.cburch.logisim.circuit.CircuitAttributes in project logisim-evolution by reds-heig.

the class Netlist method ProcessSubcircuit.

private boolean ProcessSubcircuit(Component comp, FPGAReport Reporter) {
    NetlistComponent Subcircuit = new NetlistComponent(comp);
    SubcircuitFactory sub = (SubcircuitFactory) comp.getFactory();
    Instance[] subPins = ((CircuitAttributes) comp.getAttributeSet()).getPinInstances();
    Netlist subNetlist = sub.getSubcircuit().getNetList();
    for (EndData ThisPin : comp.getEnds()) {
        Net Connection = FindConnectedNet(ThisPin.getLocation());
        int PinId = comp.getEnds().indexOf(ThisPin);
        int SubPortIndex = subNetlist.GetPortInfo(subPins[PinId].getAttributeValue(StdAttr.LABEL));
        if (SubPortIndex < 0) {
            Reporter.AddFatalError("BUG:  Unable to find pin in sub-circuit\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
            return false;
        }
        if (Connection != null) {
            boolean PinIsSink = ThisPin.isInput();
            Net RootNet = GetRootNet(Connection);
            if (RootNet == null) {
                Reporter.AddFatalError("BUG:  Unable to find a root net for sub-circuit\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
                return false;
            }
            for (byte bitid = 0; bitid < ThisPin.getWidth().getWidth(); bitid++) {
                Byte RootNetBitIndex = GetRootNetIndex(Connection, bitid);
                if (RootNetBitIndex < 0) {
                    Reporter.AddFatalError("BUG:  Unable to find a root-net bit-index for sub-circuit\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
                    return false;
                }
                Subcircuit.getEnd(PinId).GetConnection(bitid).SetParrentNet(RootNet, RootNetBitIndex);
                if (PinIsSink) {
                    RootNet.addSink(RootNetBitIndex, Subcircuit.getEnd(PinId).GetConnection(bitid));
                } else {
                    RootNet.addSource(RootNetBitIndex, Subcircuit.getEnd(PinId).GetConnection(bitid));
                }
                /*
					 * Special handling for sub-circuits; we have to find out
					 * the connection to the corresponding net in the underlying
					 * net-list; At this point the underlying net-lists have
					 * already been generated.
					 */
                Subcircuit.getEnd(PinId).GetConnection(bitid).setChildsPortIndex(SubPortIndex);
            }
        } else {
            for (byte bitid = 0; bitid < ThisPin.getWidth().getWidth(); bitid++) {
                Subcircuit.getEnd(PinId).GetConnection(bitid).setChildsPortIndex(SubPortIndex);
            }
        }
    }
    MySubCircuits.add(Subcircuit);
    return true;
}
Also used : EndData(com.cburch.logisim.comp.EndData) CircuitAttributes(com.cburch.logisim.circuit.CircuitAttributes) Instance(com.cburch.logisim.instance.Instance) SubcircuitFactory(com.cburch.logisim.circuit.SubcircuitFactory)

Aggregations

CircuitAttributes (com.cburch.logisim.circuit.CircuitAttributes)1 SubcircuitFactory (com.cburch.logisim.circuit.SubcircuitFactory)1 EndData (com.cburch.logisim.comp.EndData)1 Instance (com.cburch.logisim.instance.Instance)1