use of com.cburch.logisim.circuit.Wire in project logisim-evolution by reds-heig.
the class Netlist method GetGatedClockComponents.
public void GetGatedClockComponents(ArrayList<Netlist> HierarchyNetlists, NetlistComponent SubCircuit, Map<String, Map<NetlistComponent, Circuit>> NotGatedSet, Map<String, Map<NetlistComponent, Circuit>> GatedSet, Set<NetlistComponent> WarnedComponents, FPGAReport Reporter) {
/* First pass: we go down the tree */
for (NetlistComponent SubCirc : MySubCircuits) {
SubcircuitFactory sub = (SubcircuitFactory) SubCirc.GetComponent().getFactory();
ArrayList<String> NewHierarchyNames = new ArrayList<String>();
ArrayList<Netlist> NewHierarchyNetlists = new ArrayList<Netlist>();
NewHierarchyNames.addAll(GetCurrentHierarchyLevel());
NewHierarchyNames.add(CorrectLabel.getCorrectLabel(SubCirc.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)));
NewHierarchyNetlists.addAll(HierarchyNetlists);
NewHierarchyNetlists.add(sub.getSubcircuit().getNetList());
sub.getSubcircuit().getNetList().SetCurrentHierarchyLevel(NewHierarchyNames);
sub.getSubcircuit().getNetList().GetGatedClockComponents(NewHierarchyNetlists, SubCirc, NotGatedSet, GatedSet, WarnedComponents, Reporter);
}
/* Second pass: we find all components with a clock input and see if they are connected to a clock */
boolean GatedClock = false;
List<SourceInfo> PinSources = new ArrayList<SourceInfo>();
List<Set<Wire>> PinWires = new ArrayList<Set<Wire>>();
List<Set<NetlistComponent>> PinGatedComponents = new ArrayList<Set<NetlistComponent>>();
List<SourceInfo> NonPinSources = new ArrayList<SourceInfo>();
List<Set<Wire>> NonPinWires = new ArrayList<Set<Wire>>();
List<Set<NetlistComponent>> NonPinGatedComponents = new ArrayList<Set<NetlistComponent>>();
for (NetlistComponent comp : MyComponents) {
ComponentFactory fact = comp.GetComponent().getFactory();
if (fact instanceof DFlipFlop || fact instanceof JKFlipFlop || fact instanceof SRFlipFlop || fact instanceof TFlipFlop) {
AttributeSet attrs = comp.GetComponent().getAttributeSet();
if (IsFlipFlop(attrs)) {
GatedClock |= HasGatedClock(comp, comp.NrOfEnds() - 5, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
}
} else if (fact instanceof Counter) {
GatedClock |= HasGatedClock(comp, Counter.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
} else if (fact instanceof Ram) {
if (IsFlipFlop(comp.GetComponent().getAttributeSet()))
GatedClock |= HasGatedClock(comp, Ram.CLK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
} else if (fact instanceof Random) {
GatedClock |= HasGatedClock(comp, Random.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
} else if (fact instanceof Register) {
if (IsFlipFlop(comp.GetComponent().getAttributeSet()))
GatedClock |= HasGatedClock(comp, Register.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
} else if (fact instanceof ShiftRegister) {
GatedClock |= HasGatedClock(comp, ShiftRegister.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
}
}
/* We have two situations:
* 1) The gated clock net is generated locally, in this case we can mark them and add the current system to the non-gated set as
* each instance will be equal at higher/lower levels.
* 2) The gated clock nets are connected to a pin, in this case each instance of this circuit could be either gated or non-gated,
* we have to do something on the level higher and we mark this in the sets to be processed later.
*/
String MyName = CorrectLabel.getCorrectLabel(CircuitName);
if (HierarchyNetlists.size() > 1) {
if (GatedClock && PinSources.isEmpty()) {
GatedClock = false;
/* we have only non-pin driven gated clocks */
WarningForGatedClock(NonPinSources, NonPinGatedComponents, NonPinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_GatedClock"));
}
if (GatedClock && !PinSources.isEmpty()) {
for (int i = 0; i < PinSources.size(); i++) {
Reporter.AddSevereWarning(Strings.get("NetList_GatedClock"));
Reporter.AddWarningIncrement(Strings.get("NetList_TraceListBegin"));
SimpleDRCContainer warn = new SimpleDRCContainer(MyCircuit, Strings.get("NetList_GatedClockSink"), SimpleDRCContainer.LEVEL_NORMAL, SimpleDRCContainer.MARK_INSTANCE | SimpleDRCContainer.MARK_WIRE, true);
warn.AddMarkComponents(PinWires.get(i));
for (NetlistComponent comp : PinGatedComponents.get(i)) warn.AddMarkComponent(comp.GetComponent());
Reporter.AddWarning(warn);
WarningTraceForGatedClock(PinSources.get(i).getSource(), PinSources.get(i).getIndex(), HierarchyNetlists, CurrentHierarchyLevel, Reporter);
Reporter.AddWarningIncrement(Strings.get("NetList_TraceListEnd"));
}
}
/* we only mark if we are not at top-level */
if (GatedClock) {
if (GatedSet.containsKey(MyName))
GatedSet.get(MyName).put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
else {
Map<NetlistComponent, Circuit> newList = new HashMap<NetlistComponent, Circuit>();
newList.put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
GatedSet.put(MyName, newList);
}
} else {
if (NotGatedSet.containsKey(MyName))
NotGatedSet.get(MyName).put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
else {
Map<NetlistComponent, Circuit> newList = new HashMap<NetlistComponent, Circuit>();
newList.put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
NotGatedSet.put(MyName, newList);
}
}
} else {
/* At toplevel we warn for all possible gated clocks */
WarningForGatedClock(NonPinSources, NonPinGatedComponents, NonPinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_GatedClock"));
WarningForGatedClock(PinSources, PinGatedComponents, PinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_PossibleGatedClock"));
}
}
use of com.cburch.logisim.circuit.Wire in project logisim-evolution by reds-heig.
the class Netlist method HasGatedClock.
private boolean HasGatedClock(NetlistComponent comp, int ClockPinIndex, List<SourceInfo> PinSources, List<Set<Wire>> PinWires, List<Set<NetlistComponent>> PinGatedComponents, List<SourceInfo> NonPinSources, List<Set<Wire>> NonPinWires, List<Set<NetlistComponent>> NonPinGatedComponents, Set<NetlistComponent> WarnedComponents, FPGAReport Reporter) {
boolean GatedClock = false;
String ClockNetName = AbstractHDLGeneratorFactory.GetClockNetName(comp, ClockPinIndex, this);
if (ClockNetName.isEmpty()) {
/* we search for the source in case it is connected otherwise we ignore */
ConnectionPoint connection = comp.getEnd(ClockPinIndex).GetConnection((byte) 0);
Net connectedNet = connection.GetParrentNet();
byte connectedNetindex = connection.GetParrentNetBitIndex();
if (connectedNet != null) {
GatedClock = true;
if (connectedNet.IsForcedRootNet()) {
Set<Wire> Segments = new HashSet<Wire>();
Location loc = comp.GetComponent().getEnd(ClockPinIndex).getLocation();
for (Net thisOne : MyNets) if (thisOne.contains(loc)) {
if (!thisOne.IsRootNet())
Segments.addAll(thisOne.getWires());
}
SourceInfo SourceList = GetHiddenSource(connectedNet, connectedNetindex, MyComplexSplitters, null, new HashSet<String>(), Segments, Reporter);
ConnectionPoint source = SourceList.getSource();
if (source.GetComp().getFactory() instanceof Pin) {
int index = IndexOfEntry(PinSources, source, (int) connectedNetindex);
if (index < 0) {
PinSources.add(SourceList);
PinWires.add(Segments);
Set<NetlistComponent> comps = new HashSet<NetlistComponent>();
comps.add(comp);
comps.add(new NetlistComponent(source.GetComp()));
PinGatedComponents.add(comps);
} else {
PinGatedComponents.get(index).add(comp);
}
} else {
int index = IndexOfEntry(NonPinSources, source, (int) connectedNetindex);
if (index < 0) {
NonPinSources.add(SourceList);
NonPinWires.add(Segments);
Set<NetlistComponent> comps = new HashSet<NetlistComponent>();
comps.add(comp);
NonPinGatedComponents.add(comps);
} else {
NonPinGatedComponents.get(index).add(comp);
}
}
} else {
ArrayList<ConnectionPoint> SourceList = connectedNet.GetBitSources(connectedNetindex);
if (SourceList.size() != 1) {
Reporter.AddFatalError("BUG: Found multiple sources\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
return GatedClock;
}
ConnectionPoint source = SourceList.get(0);
if (source.GetComp().getFactory() instanceof Pin) {
int index = IndexOfEntry(PinSources, source, (int) connectedNetindex);
if (index < 0) {
SourceInfo NewEntry = new SourceInfo(source, connectedNetindex);
PinSources.add(NewEntry);
PinWires.add(connectedNet.getWires());
Set<NetlistComponent> comps = new HashSet<NetlistComponent>();
comps.add(comp);
PinGatedComponents.add(comps);
} else {
PinGatedComponents.get(index).add(comp);
}
} else {
int index = IndexOfEntry(NonPinSources, source, (int) connectedNetindex);
if (index < 0) {
SourceInfo NewEntry = new SourceInfo(source, connectedNetindex);
NonPinSources.add(NewEntry);
NonPinWires.add(connectedNet.getWires());
Set<NetlistComponent> comps = new HashSet<NetlistComponent>();
comps.add(comp);
NonPinGatedComponents.add(comps);
} else {
NonPinGatedComponents.get(index).add(comp);
}
}
}
} else {
/* Add severe warning, we found a memory with an unconnected clock input */
if (!WarnedComponents.contains(comp)) {
SimpleDRCContainer warn = new SimpleDRCContainer(MyCircuit, Strings.get("NetList_NoClockConnection"), SimpleDRCContainer.LEVEL_SEVERE, SimpleDRCContainer.MARK_INSTANCE);
warn.AddMarkComponent(comp.GetComponent());
Reporter.AddWarning(warn);
WarnedComponents.add(comp);
}
}
}
return GatedClock;
}
use of com.cburch.logisim.circuit.Wire in project logisim-evolution by reds-heig.
the class Netlist method GetNet.
private void GetNet(Wire wire, Net ThisNet) {
Iterator<Wire> MyIterator = wires.iterator();
ArrayList<Wire> MatchedWires = new ArrayList<Wire>();
Wire CompWire = wire;
while (MyIterator.hasNext()) {
Wire ThisWire = MyIterator.next();
if (CompWire == null) {
CompWire = ThisWire;
ThisNet.add(ThisWire);
MyIterator.remove();
} else if (ThisWire.sharesEnd(CompWire)) {
MatchedWires.add(ThisWire);
ThisNet.add(ThisWire);
MyIterator.remove();
}
}
for (Wire matched : MatchedWires) GetNet(matched, ThisNet);
MatchedWires.clear();
}
use of com.cburch.logisim.circuit.Wire in project logisim-evolution by reds-heig.
the class SelectionActions method getReplacementMap.
private static HashMap<Component, Component> getReplacementMap(Project proj) {
HashMap<Component, Component> replMap;
replMap = new HashMap<Component, Component>();
LogisimFile file = proj.getLogisimFile();
ArrayList<Library> libs = new ArrayList<Library>();
libs.add(file);
libs.addAll(file.getLibraries());
ArrayList<String> dropped = null;
Clipboard clip = Clipboard.get();
Collection<Component> comps = clip.getComponents();
HashMap<ComponentFactory, ComponentFactory> factoryReplacements;
factoryReplacements = new HashMap<ComponentFactory, ComponentFactory>();
for (Component comp : comps) {
if (comp instanceof Wire)
continue;
ComponentFactory compFactory = comp.getFactory();
ComponentFactory copyFactory = findComponentFactory(compFactory, libs, false);
if (factoryReplacements.containsKey(compFactory)) {
copyFactory = factoryReplacements.get(compFactory);
} else if (copyFactory == null) {
ComponentFactory candidate = findComponentFactory(compFactory, libs, true);
if (candidate == null) {
if (dropped == null) {
dropped = new ArrayList<String>();
}
dropped.add(compFactory.getDisplayName());
} else {
String msg = Strings.get("pasteCloneQuery", compFactory.getName());
Object[] opts = { Strings.get("pasteCloneReplace"), Strings.get("pasteCloneIgnore"), Strings.get("pasteCloneCancel") };
int select = JOptionPane.showOptionDialog(proj.getFrame(), msg, Strings.get("pasteCloneTitle"), 0, JOptionPane.QUESTION_MESSAGE, null, opts, opts[0]);
if (select == 0) {
copyFactory = candidate;
} else if (select == 1) {
copyFactory = null;
} else {
return null;
}
factoryReplacements.put(compFactory, copyFactory);
}
}
if (copyFactory == null) {
replMap.put(comp, null);
} else if (copyFactory != compFactory) {
Location copyLoc = comp.getLocation();
AttributeSet copyAttrs = (AttributeSet) comp.getAttributeSet().clone();
Component copy = copyFactory.createComponent(copyLoc, copyAttrs);
replMap.put(comp, copy);
}
}
if (dropped != null) {
Collections.sort(dropped);
StringBuilder droppedStr = new StringBuilder();
droppedStr.append(Strings.get("pasteDropMessage"));
String curName = dropped.get(0);
int curCount = 1;
int lines = 1;
for (int i = 1; i <= dropped.size(); i++) {
String nextName = i == dropped.size() ? "" : dropped.get(i);
if (nextName.equals(curName)) {
curCount++;
} else {
lines++;
droppedStr.append("\n ");
droppedStr.append(curName);
if (curCount > 1) {
droppedStr.append(" \u00d7 " + curCount);
}
curName = nextName;
curCount = 1;
}
}
lines = Math.max(3, Math.min(7, lines));
JTextArea area = new JTextArea(lines, 60);
area.setEditable(false);
area.setText(droppedStr.toString());
area.setCaretPosition(0);
JScrollPane areaPane = new JScrollPane(area);
JOptionPane.showMessageDialog(proj.getFrame(), areaPane, Strings.get("pasteDropTitle"), JOptionPane.WARNING_MESSAGE);
}
return replMap;
}
use of com.cburch.logisim.circuit.Wire in project logisim-evolution by reds-heig.
the class XmlWriter method fromCircuit.
Element fromCircuit(Circuit circuit) {
Element ret = doc.createElement("circuit");
ret.setAttribute("name", circuit.getName());
addAttributeSetContent(ret, circuit.getStaticAttributes(), null);
if (!circuit.getAppearance().isDefaultAppearance()) {
Element appear = doc.createElement("appear");
for (Object o : circuit.getAppearance().getObjectsFromBottom()) {
if (o instanceof AbstractCanvasObject) {
Element elt = ((AbstractCanvasObject) o).toSvgElement(doc);
if (elt != null) {
appear.appendChild(elt);
}
}
}
ret.appendChild(appear);
}
for (Wire w : circuit.getWires()) {
ret.appendChild(fromWire(w));
}
for (Component comp : circuit.getNonWires()) {
Element elt = fromComponent(comp);
if (elt != null)
ret.appendChild(elt);
}
return ret;
}
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