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Example 1 with DFlipFlop

use of com.cburch.logisim.std.memory.DFlipFlop in project logisim-evolution by reds-heig.

the class Netlist method GetGatedClockComponents.

public void GetGatedClockComponents(ArrayList<Netlist> HierarchyNetlists, NetlistComponent SubCircuit, Map<String, Map<NetlistComponent, Circuit>> NotGatedSet, Map<String, Map<NetlistComponent, Circuit>> GatedSet, Set<NetlistComponent> WarnedComponents, FPGAReport Reporter) {
    /* First pass: we go down the tree */
    for (NetlistComponent SubCirc : MySubCircuits) {
        SubcircuitFactory sub = (SubcircuitFactory) SubCirc.GetComponent().getFactory();
        ArrayList<String> NewHierarchyNames = new ArrayList<String>();
        ArrayList<Netlist> NewHierarchyNetlists = new ArrayList<Netlist>();
        NewHierarchyNames.addAll(GetCurrentHierarchyLevel());
        NewHierarchyNames.add(CorrectLabel.getCorrectLabel(SubCirc.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)));
        NewHierarchyNetlists.addAll(HierarchyNetlists);
        NewHierarchyNetlists.add(sub.getSubcircuit().getNetList());
        sub.getSubcircuit().getNetList().SetCurrentHierarchyLevel(NewHierarchyNames);
        sub.getSubcircuit().getNetList().GetGatedClockComponents(NewHierarchyNetlists, SubCirc, NotGatedSet, GatedSet, WarnedComponents, Reporter);
    }
    /* Second pass: we find all components with a clock input and see if they are connected to a clock */
    boolean GatedClock = false;
    List<SourceInfo> PinSources = new ArrayList<SourceInfo>();
    List<Set<Wire>> PinWires = new ArrayList<Set<Wire>>();
    List<Set<NetlistComponent>> PinGatedComponents = new ArrayList<Set<NetlistComponent>>();
    List<SourceInfo> NonPinSources = new ArrayList<SourceInfo>();
    List<Set<Wire>> NonPinWires = new ArrayList<Set<Wire>>();
    List<Set<NetlistComponent>> NonPinGatedComponents = new ArrayList<Set<NetlistComponent>>();
    for (NetlistComponent comp : MyComponents) {
        ComponentFactory fact = comp.GetComponent().getFactory();
        if (fact instanceof DFlipFlop || fact instanceof JKFlipFlop || fact instanceof SRFlipFlop || fact instanceof TFlipFlop) {
            AttributeSet attrs = comp.GetComponent().getAttributeSet();
            if (IsFlipFlop(attrs)) {
                GatedClock |= HasGatedClock(comp, comp.NrOfEnds() - 5, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
            }
        } else if (fact instanceof Counter) {
            GatedClock |= HasGatedClock(comp, Counter.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
        } else if (fact instanceof Ram) {
            if (IsFlipFlop(comp.GetComponent().getAttributeSet()))
                GatedClock |= HasGatedClock(comp, Ram.CLK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
        } else if (fact instanceof Random) {
            GatedClock |= HasGatedClock(comp, Random.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
        } else if (fact instanceof Register) {
            if (IsFlipFlop(comp.GetComponent().getAttributeSet()))
                GatedClock |= HasGatedClock(comp, Register.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
        } else if (fact instanceof ShiftRegister) {
            GatedClock |= HasGatedClock(comp, ShiftRegister.CK, PinSources, PinWires, PinGatedComponents, NonPinSources, NonPinWires, NonPinGatedComponents, WarnedComponents, Reporter);
        }
    }
    /* We have two situations:
		 * 1) The gated clock net is generated locally, in this case we can mark them and add the current system to the non-gated set as
		 *    each instance will be equal at higher/lower levels.
		 * 2) The gated clock nets are connected to a pin, in this case each instance of this circuit could be either gated or non-gated,
		 *    we have to do something on the level higher and we mark this in the sets to be processed later. 
		 */
    String MyName = CorrectLabel.getCorrectLabel(CircuitName);
    if (HierarchyNetlists.size() > 1) {
        if (GatedClock && PinSources.isEmpty()) {
            GatedClock = false;
            /* we have only non-pin driven gated clocks */
            WarningForGatedClock(NonPinSources, NonPinGatedComponents, NonPinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_GatedClock"));
        }
        if (GatedClock && !PinSources.isEmpty()) {
            for (int i = 0; i < PinSources.size(); i++) {
                Reporter.AddSevereWarning(Strings.get("NetList_GatedClock"));
                Reporter.AddWarningIncrement(Strings.get("NetList_TraceListBegin"));
                SimpleDRCContainer warn = new SimpleDRCContainer(MyCircuit, Strings.get("NetList_GatedClockSink"), SimpleDRCContainer.LEVEL_NORMAL, SimpleDRCContainer.MARK_INSTANCE | SimpleDRCContainer.MARK_WIRE, true);
                warn.AddMarkComponents(PinWires.get(i));
                for (NetlistComponent comp : PinGatedComponents.get(i)) warn.AddMarkComponent(comp.GetComponent());
                Reporter.AddWarning(warn);
                WarningTraceForGatedClock(PinSources.get(i).getSource(), PinSources.get(i).getIndex(), HierarchyNetlists, CurrentHierarchyLevel, Reporter);
                Reporter.AddWarningIncrement(Strings.get("NetList_TraceListEnd"));
            }
        }
        /* we only mark if we are not at top-level */
        if (GatedClock) {
            if (GatedSet.containsKey(MyName))
                GatedSet.get(MyName).put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
            else {
                Map<NetlistComponent, Circuit> newList = new HashMap<NetlistComponent, Circuit>();
                newList.put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
                GatedSet.put(MyName, newList);
            }
        } else {
            if (NotGatedSet.containsKey(MyName))
                NotGatedSet.get(MyName).put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
            else {
                Map<NetlistComponent, Circuit> newList = new HashMap<NetlistComponent, Circuit>();
                newList.put(SubCircuit, HierarchyNetlists.get(HierarchyNetlists.size() - 2).getCircuit());
                NotGatedSet.put(MyName, newList);
            }
        }
    } else {
        /* At toplevel we warn for all possible gated clocks */
        WarningForGatedClock(NonPinSources, NonPinGatedComponents, NonPinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_GatedClock"));
        WarningForGatedClock(PinSources, PinGatedComponents, PinWires, WarnedComponents, HierarchyNetlists, Reporter, Strings.get("NetList_PossibleGatedClock"));
    }
}
Also used : DFlipFlop(com.cburch.logisim.std.memory.DFlipFlop) HashSet(java.util.HashSet) Set(java.util.Set) AttributeSet(com.cburch.logisim.data.AttributeSet) HashMap(java.util.HashMap) ComponentFactory(com.cburch.logisim.comp.ComponentFactory) ArrayList(java.util.ArrayList) TFlipFlop(com.cburch.logisim.std.memory.TFlipFlop) ShiftRegister(com.cburch.logisim.std.memory.ShiftRegister) Wire(com.cburch.logisim.circuit.Wire) Counter(com.cburch.logisim.std.memory.Counter) SRFlipFlop(com.cburch.logisim.std.memory.SRFlipFlop) Random(com.cburch.logisim.std.memory.Random) SubcircuitFactory(com.cburch.logisim.circuit.SubcircuitFactory) JKFlipFlop(com.cburch.logisim.std.memory.JKFlipFlop) Circuit(com.cburch.logisim.circuit.Circuit) AttributeSet(com.cburch.logisim.data.AttributeSet) ShiftRegister(com.cburch.logisim.std.memory.ShiftRegister) Register(com.cburch.logisim.std.memory.Register) Ram(com.cburch.logisim.std.memory.Ram)

Aggregations

Circuit (com.cburch.logisim.circuit.Circuit)1 SubcircuitFactory (com.cburch.logisim.circuit.SubcircuitFactory)1 Wire (com.cburch.logisim.circuit.Wire)1 ComponentFactory (com.cburch.logisim.comp.ComponentFactory)1 AttributeSet (com.cburch.logisim.data.AttributeSet)1 Counter (com.cburch.logisim.std.memory.Counter)1 DFlipFlop (com.cburch.logisim.std.memory.DFlipFlop)1 JKFlipFlop (com.cburch.logisim.std.memory.JKFlipFlop)1 Ram (com.cburch.logisim.std.memory.Ram)1 Random (com.cburch.logisim.std.memory.Random)1 Register (com.cburch.logisim.std.memory.Register)1 SRFlipFlop (com.cburch.logisim.std.memory.SRFlipFlop)1 ShiftRegister (com.cburch.logisim.std.memory.ShiftRegister)1 TFlipFlop (com.cburch.logisim.std.memory.TFlipFlop)1 ArrayList (java.util.ArrayList)1 HashMap (java.util.HashMap)1 HashSet (java.util.HashSet)1 Set (java.util.Set)1