use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class CounterHDLGeneratorFactory method GetParameterMap.
@Override
public SortedMap<String, Integer> GetParameterMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter) {
SortedMap<String, Integer> ParameterMap = new TreeMap<String, Integer>();
AttributeSet attrs = ComponentInfo.GetComponent().getAttributeSet();
int mode = 0;
if (attrs.containsAttribute(Counter.ATTR_ON_GOAL)) {
if (attrs.getValue(Counter.ATTR_ON_GOAL) == Counter.ON_GOAL_STAY)
mode = 1;
else if (attrs.getValue(Counter.ATTR_ON_GOAL) == Counter.ON_GOAL_CONT)
mode = 2;
else if (attrs.getValue(Counter.ATTR_ON_GOAL) == Counter.ON_GOAL_LOAD)
mode = 3;
} else {
mode = 1;
}
ParameterMap.put(NrOfBitsStr, attrs.getValue(StdAttr.WIDTH).getWidth());
ParameterMap.put(MaxValStr, attrs.getValue(Counter.ATTR_MAX).intValue());
int ClkEdge = 1;
if (GetClockNetName(ComponentInfo, Counter.CK, Nets).isEmpty() && attrs.getValue(StdAttr.EDGE_TRIGGER) == StdAttr.TRIG_FALLING)
ClkEdge = 0;
ParameterMap.put(ActiveEdgeStr, ClkEdge);
ParameterMap.put(ModeStr, mode);
return ParameterMap;
}
use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class CounterHDLGeneratorFactory method GetPortMap.
@Override
public SortedMap<String, String> GetPortMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter, String HDLType) {
SortedMap<String, String> PortMap = new TreeMap<String, String>();
String ZeroBit = (HDLType.equals(VHDL)) ? "'0'" : "1'b0";
String SetBit = (HDLType.equals(VHDL)) ? "'1'" : "1'b1";
String BracketOpen = (HDLType.equals(VHDL)) ? "(" : "[";
String BracketClose = (HDLType.equals(VHDL)) ? ")" : "]";
AttributeSet attrs = ComponentInfo.GetComponent().getAttributeSet();
if (!ComponentInfo.EndIsConnected(Counter.CK)) {
Reporter.AddSevereWarning("Component \"Counter\" in circuit \"" + Nets.getCircuitName() + "\" has no clock connection");
PortMap.put("GlobalClock", ZeroBit);
PortMap.put("ClockEnable", ZeroBit);
} else {
String ClockNetName = GetClockNetName(ComponentInfo, Counter.CK, Nets);
if (ClockNetName.isEmpty()) {
PortMap.putAll(GetNetMap("GlobalClock", true, ComponentInfo, Counter.CK, Reporter, HDLType, Nets));
PortMap.put("ClockEnable", SetBit);
} else {
int ClockBusIndex = ClockHDLGeneratorFactory.DerivedClockIndex;
if (Nets.RequiresGlobalClockConnection()) {
ClockBusIndex = ClockHDLGeneratorFactory.GlobalClockIndex;
} else {
if (attrs.getValue(StdAttr.EDGE_TRIGGER) == StdAttr.TRIG_LOW)
ClockBusIndex = ClockHDLGeneratorFactory.InvertedDerivedClockIndex;
else if (attrs.getValue(StdAttr.EDGE_TRIGGER) == StdAttr.TRIG_RISING)
ClockBusIndex = ClockHDLGeneratorFactory.PositiveEdgeTickIndex;
else if (attrs.getValue(StdAttr.EDGE_TRIGGER) == StdAttr.TRIG_FALLING)
ClockBusIndex = ClockHDLGeneratorFactory.InvertedDerivedClockIndex;
}
PortMap.put("GlobalClock", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.GlobalClockIndex) + BracketClose);
PortMap.put("ClockEnable", ClockNetName + BracketOpen + Integer.toString(ClockBusIndex) + BracketClose);
}
}
String Input = "LoadData";
if (HDLType.equals(VHDL) & (ComponentInfo.GetComponent().getAttributeSet().getValue(StdAttr.WIDTH).getWidth() == 1))
Input += "(0)";
PortMap.putAll(GetNetMap(Input, true, ComponentInfo, Counter.IN, Reporter, HDLType, Nets));
PortMap.putAll(GetNetMap("clear", true, ComponentInfo, Counter.CLR, Reporter, HDLType, Nets));
PortMap.putAll(GetNetMap("load", true, ComponentInfo, Counter.LD, Reporter, HDLType, Nets));
PortMap.putAll(GetNetMap("Enable", false, ComponentInfo, Counter.EN, Reporter, HDLType, Nets));
PortMap.putAll(GetNetMap("Up_n_Down", false, ComponentInfo, Counter.UD, Reporter, HDLType, Nets));
String Output = "CountValue";
if (HDLType.equals(VHDL) & (ComponentInfo.GetComponent().getAttributeSet().getValue(StdAttr.WIDTH).getWidth() == 1))
Output += "(0)";
PortMap.putAll(GetNetMap(Output, true, ComponentInfo, Counter.OUT, Reporter, HDLType, Nets));
PortMap.putAll(GetNetMap("CompareOut", true, ComponentInfo, Counter.CARRY, Reporter, HDLType, Nets));
return PortMap;
}
use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class ShiftRegisterHDLGeneratorFactory method GetParameterMap.
@Override
public SortedMap<String, Integer> GetParameterMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter) {
SortedMap<String, Integer> ParameterMap = new TreeMap<String, Integer>();
AttributeSet attrs = ComponentInfo.GetComponent().getAttributeSet();
int ActiveLevel = 1;
Boolean GatedClock = false;
Boolean ActiveLow = false;
String ClockNetName = GetClockNetName(ComponentInfo, ShiftRegister.CK, Nets);
if (ClockNetName.isEmpty()) {
GatedClock = true;
}
ActiveLow = attrs.getValue(StdAttr.EDGE_TRIGGER) == StdAttr.TRIG_FALLING;
if (GatedClock && ActiveLow) {
ActiveLevel = 0;
}
int NrOfBits = attrs.getValue(StdAttr.WIDTH).getWidth();
int NrOfStages = attrs.getValue(ShiftRegister.ATTR_LENGTH);
ParameterMap.put(ActiveLevelStr, ActiveLevel);
ParameterMap.put(NrOfBitsStr, NrOfBits);
ParameterMap.put(NrOfStagesStr, NrOfStages);
ParameterMap.put(NrOfParBitsStr, NrOfBits * NrOfStages);
return ParameterMap;
}
use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class Ram method DrawControlBlock.
private void DrawControlBlock(InstancePainter painter, int xpos, int ypos) {
Object trigger = painter.getAttributeValue(StdAttr.TRIGGER);
boolean asynch = trigger.equals(StdAttr.TRIG_HIGH) || trigger.equals(StdAttr.TRIG_LOW);
boolean inverted = trigger.equals(StdAttr.TRIG_FALLING) || trigger.equals(StdAttr.TRIG_LOW);
Object be = painter.getAttributeValue(RamAttributes.ATTR_ByteEnables);
boolean byteEnables = be == null ? false : be.equals(RamAttributes.BUS_WITH_BYTEENABLES);
int NrOfByteEnables = GetNrOfByteEnables(painter.getAttributeSet());
Graphics g = painter.getGraphics();
GraphicsUtil.switchToWidth(g, 2);
AttributeSet attrs = painter.getAttributeSet();
g.drawLine(xpos + 20, ypos, xpos + 20 + SymbolWidth, ypos);
g.drawLine(xpos + 20, ypos, xpos + 20, ypos + getControlHeight(attrs) - 10);
g.drawLine(xpos + 20 + SymbolWidth, ypos, xpos + 20 + SymbolWidth, ypos + getControlHeight(attrs) - 10);
g.drawLine(xpos + 20, ypos + getControlHeight(attrs) - 10, xpos + 30, ypos + getControlHeight(attrs) - 10);
g.drawLine(xpos + 20 + SymbolWidth - 10, ypos + getControlHeight(attrs) - 10, xpos + 20 + SymbolWidth, ypos + getControlHeight(attrs) - 10);
g.drawLine(xpos + 30, ypos + getControlHeight(attrs) - 10, xpos + 30, ypos + getControlHeight(attrs));
g.drawLine(xpos + 20 + SymbolWidth - 10, ypos + getControlHeight(attrs) - 10, xpos + 20 + SymbolWidth - 10, ypos + getControlHeight(attrs));
GraphicsUtil.drawCenteredText(g, "RAM " + GetSizeLabel(painter.getAttributeValue(Mem.ADDR_ATTR).getWidth()) + " x " + Integer.toString(painter.getAttributeValue(Mem.DATA_ATTR).getWidth()), xpos + (SymbolWidth / 2) + 20, ypos + 5);
if (asynch && inverted) {
g.drawLine(xpos, ypos + 50, xpos + 12, ypos + 50);
g.drawOval(xpos + 12, ypos + 46, 8, 8);
} else {
g.drawLine(xpos, ypos + 50, xpos + 20, ypos + 50);
}
GraphicsUtil.drawText(g, "M1 [Write Enable]", xpos + 33, ypos + 50, GraphicsUtil.H_LEFT, GraphicsUtil.V_CENTER);
painter.drawPort(WE);
if (asynch && inverted) {
g.drawLine(xpos, ypos + 60, xpos + 12, ypos + 60);
g.drawOval(xpos + 12, ypos + 56, 8, 8);
} else {
g.drawLine(xpos, ypos + 60, xpos + 20, ypos + 60);
}
GraphicsUtil.drawText(g, "M2 [Output Enable]", xpos + 33, ypos + 60, GraphicsUtil.H_LEFT, GraphicsUtil.V_CENTER);
painter.drawPort(OE);
if (!asynch) {
int yoffset = 70;
if (byteEnables) {
yoffset += NrOfByteEnables * 10;
}
if (inverted) {
g.drawLine(xpos, ypos + yoffset, xpos + 12, ypos + yoffset);
g.drawOval(xpos + 12, ypos + yoffset - 4, 8, 8);
} else {
g.drawLine(xpos, ypos + yoffset, xpos + 20, ypos + yoffset);
}
GraphicsUtil.drawText(g, "C3", xpos + 33, ypos + yoffset, GraphicsUtil.H_LEFT, GraphicsUtil.V_CENTER);
painter.drawClockSymbol(xpos + 20, ypos + yoffset);
painter.drawPort(CLK);
}
if (byteEnables) {
int ByteEnableIndex = ByteEnableIndex(painter.getAttributeSet());
GraphicsUtil.switchToWidth(g, 2);
for (int i = 0; i < NrOfByteEnables; i++) {
g.drawLine(xpos, ypos + 70 + i * 10, xpos + 20, ypos + 70 + i * 10);
painter.drawPort(ByteEnableIndex + i);
String Label = "M" + Integer.toString((NrOfByteEnables - i) + 3) + " [ByteEnable " + Integer.toString((NrOfByteEnables - i) - 1) + "]";
GraphicsUtil.drawText(g, Label, xpos + 33, ypos + 70 + i * 10, GraphicsUtil.H_LEFT, GraphicsUtil.V_CENTER);
}
}
GraphicsUtil.switchToWidth(g, 1);
DrawAddress(painter, xpos, ypos + 10, painter.getAttributeValue(Mem.ADDR_ATTR).getWidth());
}
use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class RamState method attributeValueChanged.
@Override
public void attributeValueChanged(AttributeEvent e) {
AttributeSet attrs = e.getSource();
BitWidth addrBits = attrs.getValue(Mem.ADDR_ATTR);
BitWidth dataBits = attrs.getValue(Mem.DATA_ATTR);
getContents().setDimensions(addrBits.getWidth(), dataBits.getWidth(), false);
}
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