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Example 1 with AMD64MulDivOp

use of org.graalvm.compiler.lir.amd64.AMD64MulDivOp in project graal by oracle.

the class AMD64ArithmeticLIRGenerator method emitIDIV.

private AMD64MulDivOp emitIDIV(OperandSize size, Value a, Value b, LIRFrameState state) {
    LIRKind kind = LIRKind.combine(a, b);
    AMD64SignExtendOp sx = getLIRGen().append(new AMD64SignExtendOp(size, kind, moveToReg(AMD64.rax, a)));
    return getLIRGen().append(new AMD64MulDivOp(AMD64MOp.IDIV, size, kind, sx.getHighResult(), sx.getLowResult(), getLIRGen().asAllocatable(b), state));
}
Also used : AMD64MulDivOp(org.graalvm.compiler.lir.amd64.AMD64MulDivOp) AMD64SignExtendOp(org.graalvm.compiler.lir.amd64.AMD64SignExtendOp) LIRKind(org.graalvm.compiler.core.common.LIRKind)

Example 2 with AMD64MulDivOp

use of org.graalvm.compiler.lir.amd64.AMD64MulDivOp in project graal by oracle.

the class AMD64ArithmeticLIRGenerator method emitDIV.

private AMD64MulDivOp emitDIV(OperandSize size, Value a, Value b, LIRFrameState state) {
    LIRKind kind = LIRKind.combine(a, b);
    RegisterValue rax = moveToReg(AMD64.rax, a);
    RegisterValue rdx = AMD64.rdx.asValue(kind);
    getLIRGen().append(new AMD64ClearRegisterOp(size, rdx));
    return getLIRGen().append(new AMD64MulDivOp(AMD64MOp.DIV, size, kind, rdx, rax, getLIRGen().asAllocatable(b), state));
}
Also used : RegisterValue(jdk.vm.ci.code.RegisterValue) AMD64MulDivOp(org.graalvm.compiler.lir.amd64.AMD64MulDivOp) LIRKind(org.graalvm.compiler.core.common.LIRKind) AMD64ClearRegisterOp(org.graalvm.compiler.lir.amd64.AMD64ClearRegisterOp)

Example 3 with AMD64MulDivOp

use of org.graalvm.compiler.lir.amd64.AMD64MulDivOp in project graal by oracle.

the class AMD64ArithmeticLIRGenerator method emitDiv.

@Override
public Value emitDiv(Value a, Value b, LIRFrameState state) {
    TargetDescription target = getLIRGen().target();
    boolean isAvx = ((AMD64) target.arch).getFeatures().contains(CPUFeature.AVX);
    LIRKind resultKind = LIRKind.combine(a, b);
    switch((AMD64Kind) a.getPlatformKind()) {
        case DWORD:
            AMD64MulDivOp op = emitIDIV(DWORD, a, b, state);
            return getLIRGen().emitMove(op.getQuotient());
        case QWORD:
            AMD64MulDivOp lop = emitIDIV(QWORD, a, b, state);
            return getLIRGen().emitMove(lop.getQuotient());
        case SINGLE:
            if (isAvx) {
                return emitBinary(resultKind, AVXOp.DIV, SS, false, a, b);
            } else {
                return emitBinary(resultKind, SSEOp.DIV, SS, false, a, b);
            }
        case DOUBLE:
            if (isAvx) {
                return emitBinary(resultKind, AVXOp.DIV, SD, false, a, b);
            } else {
                return emitBinary(resultKind, SSEOp.DIV, SD, false, a, b);
            }
        default:
            throw GraalError.shouldNotReachHere();
    }
}
Also used : AMD64MulDivOp(org.graalvm.compiler.lir.amd64.AMD64MulDivOp) AMD64Kind(jdk.vm.ci.amd64.AMD64Kind) TargetDescription(jdk.vm.ci.code.TargetDescription) LIRKind(org.graalvm.compiler.core.common.LIRKind)

Aggregations

LIRKind (org.graalvm.compiler.core.common.LIRKind)3 AMD64MulDivOp (org.graalvm.compiler.lir.amd64.AMD64MulDivOp)3 AMD64Kind (jdk.vm.ci.amd64.AMD64Kind)1 RegisterValue (jdk.vm.ci.code.RegisterValue)1 TargetDescription (jdk.vm.ci.code.TargetDescription)1 AMD64ClearRegisterOp (org.graalvm.compiler.lir.amd64.AMD64ClearRegisterOp)1 AMD64SignExtendOp (org.graalvm.compiler.lir.amd64.AMD64SignExtendOp)1