Example 1 with OperationNotImplementedException
use of org.jikesrvm.compilers.opt.OperationNotImplementedException in project JikesRVM by JikesRVM.
the class AssemblerOpt method genCode.
protected final int genCode(IR ir, boolean shouldPrint) {
int mi = 0;
CodeArray machinecodes = ir.MIRInfo.machinecode;
PhysicalRegisterSet phys = ir.regpool.getPhysicalRegisterSet().asPPC();
int labelCountEstimate = ir.cfg.numberOfNodes();
branchBackPatching = new BranchInformationForBackPatching(labelCountEstimate);
boolean unsafeCondDispl = machinecodes.length() > MAX_COND_DISPL;
// boolean unsafeDispl = machinecodes.length() > MAX_DISPL;
MachineCodeOffsets mcOffsets = ir.MIRInfo.mcOffsets;
for (Instruction p = ir.firstInstructionInCodeOrder(); p != null; p = p.nextInstructionInCodeOrder()) {
int inst = p.operator().instTemplate();
switch(p.getOpcode()) {
case LABEL_opcode:
backpatchForwardBranches(p, machinecodes, mi, mcOffsets);
break;
case BBEND_opcode:
case UNINT_BEGIN_opcode:
case UNINT_END_opcode:
case GUARD_MOVE_opcode:
case GUARD_COMBINE_opcode:
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
break;
case PPC_DATA_INT_opcode:
{
int value = MIR_DataInt.getValue(p).value;
machinecodes.set(mi++, value);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_DATA_LABEL_opcode:
{
Instruction target = MIR_DataLabel.getTarget(p).target;
int targetOffset = resolveBranch(p, target, mi, mcOffsets);
machinecodes.set(mi++, targetOffset);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_CRAND_opcode:
case PPC_CRANDC_opcode:
case PPC_CROR_opcode:
case PPC_CRORC_opcode:
{
int op0 = MIR_Condition.getResultBit(p).value & REG_MASK;
int op1 = MIR_Condition.getValue1Bit(p).value & REG_MASK;
int op2 = MIR_Condition.getValue2Bit(p).value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_ADD_opcode:
case PPC_ADDr_opcode:
case PPC_ADDC_opcode:
case PPC_ADDE_opcode:
case PPC_SUBF_opcode:
case PPC_SUBFr_opcode:
case PPC_SUBFC_opcode:
case PPC_SUBFCr_opcode:
case PPC_SUBFE_opcode:
case PPC_FADD_opcode:
case PPC_FADDS_opcode:
case PPC_FDIV_opcode:
case PPC_FDIVS_opcode:
case PPC_DIVW_opcode:
case PPC_DIVWU_opcode:
case PPC_MULLW_opcode:
case PPC_MULHW_opcode:
case PPC_MULHWU_opcode:
case PPC_FSUB_opcode:
case PPC_FSUBS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_MULLD_opcode:
case PPC64_DIVD_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LWZX_opcode:
case PPC_LWARX_opcode:
case PPC_LBZX_opcode:
case PPC_LHAX_opcode:
case PPC_LHZX_opcode:
case PPC_LFDX_opcode:
case PPC_LFSX_opcode:
case PPC_LIntX_opcode:
case PPC_LAddrARX_opcode:
case PPC_LAddrX_opcode:
{
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_Load.getOffset(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_LDX_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_Load.getOffset(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_STWX_opcode:
case PPC_STWCXr_opcode:
case PPC_STBX_opcode:
case PPC_STHX_opcode:
case PPC_STFDX_opcode:
case PPC_STFSX_opcode:
case PPC_STAddrCXr_opcode:
case PPC_STAddrX_opcode:
case PPC_STAddrUX_opcode:
{
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_Store.getOffset(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LWZUX_opcode:
case PPC_LBZUX_opcode:
case PPC_LIntUX_opcode:
case PPC_LAddrUX_opcode:
{
int op0 = MIR_LoadUpdate.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_LoadUpdate.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_LoadUpdate.getOffset(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LWZU_opcode:
{
int op0 = MIR_LoadUpdate.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_LoadUpdate.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_LoadUpdate.getOffset(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_TW_opcode:
case PPC_TAddr_opcode:
{
int op0 = MIR_Trap.getCond(p).value;
int op1 = MIR_Trap.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Trap.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_TD_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Trap.getCond(p).value;
int op1 = MIR_Trap.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Trap.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_TWI_opcode:
{
int op0 = MIR_Trap.getCond(p).value;
int op1 = MIR_Trap.getValue1(p).getRegister().number & REG_MASK;
int op2;
if (VM.BuildFor64Addr && MIR_Trap.getValue2(p).isLongConstant()) {
op2 = ((int) MIR_Trap.getValue2(p).asLongConstant().value) & SHORT_MASK;
} else {
op2 = MIR_Trap.getValue2(p).asIntConstant().value & SHORT_MASK;
}
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_TDI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Trap.getCond(p).value;
int op1 = MIR_Trap.getValue1(p).getRegister().number & REG_MASK;
int op2;
if (MIR_Trap.getValue2(p).isLongConstant()) {
op2 = ((int) MIR_Trap.getValue2(p).asLongConstant().value) & SHORT_MASK;
} else {
op2 = MIR_Trap.getValue2(p).asIntConstant().value & SHORT_MASK;
}
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case NULL_CHECK_opcode:
/* Just a nicer name for a twi <ref> lessthan 1 */
{
int op0 = PowerPCTrapOperand.LOWER;
int op1 = ((RegisterOperand) NullCheck.getRef(p)).getRegister().number & REG_MASK;
int op2 = 1;
inst = VM.BuildFor64Addr ? PPC64_TDI.instTemplate() : PPC_TWI.instTemplate();
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LDI_opcode:
case PPC_LDIS_opcode:
// D_Form. pseudo instructions derived from PPC_ADDI and PPC_ADDIS
{
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_ADDIC_opcode:
case PPC_ADDICr_opcode:
case PPC_SUBFIC_opcode:
case PPC_MULLI_opcode:
case PPC_ADDI_opcode:
case PPC_ADDIS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_CNTLZW_opcode:
case PPC_CNTLZAddr_opcode:
case PPC_EXTSB_opcode:
case PPC_EXTSBr_opcode:
case PPC_EXTSH_opcode:
case PPC_EXTSHr_opcode:
{
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_EXTSW_opcode:
case PPC64_EXTSWr_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_EXTZW_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
// op3low = 0, so op3 == 32
int op3high = 1;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_ADDZE_opcode:
case PPC_SUBFZE_opcode:
case PPC_NEG_opcode:
case PPC_NEGr_opcode:
case PPC_ADDME_opcode:
{
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
// Bit positions of op1 and op2 are reversed.
case PPC_XORI_opcode:
case PPC_XORIS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
// Bit positions of op1 and op2 are reversed.
case PPC_AND_opcode:
case PPC_ANDr_opcode:
case PPC_NAND_opcode:
case PPC_NANDr_opcode:
case PPC_ANDC_opcode:
case PPC_ANDCr_opcode:
case PPC_OR_opcode:
case PPC_ORr_opcode:
case PPC_NOR_opcode:
case PPC_NORr_opcode:
case PPC_ORC_opcode:
case PPC_ORCr_opcode:
case PPC_XOR_opcode:
case PPC_XORr_opcode:
case PPC_EQV_opcode:
case PPC_EQVr_opcode:
case PPC_SLW_opcode:
case PPC_SLWr_opcode:
case PPC_SRW_opcode:
case PPC_SRWr_opcode:
case PPC_SRAW_opcode:
case PPC_SRAWr_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_SLD_opcode:
case PPC64_SLDr_opcode:
case PPC64_SRD_opcode:
case PPC64_SRDr_opcode:
case PPC64_SRAD_opcode:
case PPC64_SRADr_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_MOVE_opcode:
/* pseudo opcode, equal to PPC_ORI with 0 */
{
int op0 = MIR_Move.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Move.getValue(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_SRWI_opcode:
/* pseudo opcode, equal to rlwinm Rx,Ry,32-n,n,31 */
case PPC_SRWIr_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int shift = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
int op2 = (32 - shift);
int op3 = shift;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
// Bit positions of op1 and op2 are reversed.
case PPC_SLWI_opcode:
case PPC_SLWIr_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int shift = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
int op2 = shift;
int op3 = (31 - shift);
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_SRAWI_opcode:
case PPC_SRAWIr_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_SRAddrI_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int shift = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
int op2 = (32 - shift);
int op3 = shift;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op3 = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2 = 64 - op3;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC_SRAAddrI_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC64_SRADI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_SRDI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op3 = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2 = 64 - op3;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case // shorthand via RLDICR
PPC64_SLDI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int shift = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2 = shift;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
int op3 = 63 - shift;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_RLDICR_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
// shift
int op2 = MIR_RotateAndMask.getShift(p).asIntConstant().value & SIXBIT_MASK;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
// mask
int op3 = MIR_RotateAndMask.getMaskEnd(p).value & SIXBIT_MASK;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
if (VM.VerifyAssertions) {
int op4 = MIR_RotateAndMask.getMaskBegin(p).value & SIXBIT_MASK;
VM._assert(op4 == 0);
}
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_RLDICL_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
// shift
int op2 = MIR_RotateAndMask.getShift(p).asIntConstant().value & SIXBIT_MASK;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
// mask
int op3 = MIR_RotateAndMask.getMaskBegin(p).value & SIXBIT_MASK;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
if (VM.VerifyAssertions) {
int op4 = MIR_RotateAndMask.getMaskEnd(p).value & SIXBIT_MASK;
VM._assert(op4 == 63);
}
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
// Bit positions of op1 and op2 are reversed.
case PPC_ANDIr_opcode:
case PPC_ANDISr_opcode:
case PPC_ORI_opcode:
case PPC_ORIS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_RLWINM_opcode:
case PPC_RLWINMr_opcode:
{
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
int op2 = MIR_RotateAndMask.getShift(p).asIntConstant().value & REG_MASK;
int op3 = MIR_RotateAndMask.getMaskBegin(p).value & REG_MASK;
int op4 = MIR_RotateAndMask.getMaskEnd(p).value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6) | (op4 << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_RLWIMI_opcode:
case PPC_RLWIMIr_opcode:
{
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op0f = MIR_RotateAndMask.getSource(p).getRegister().number & REG_MASK;
if (op0 != op0f) {
throw new OptimizingCompilerException("CodeGen", "format for RLWIMI is incorrect");
}
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
int op2 = MIR_RotateAndMask.getShift(p).asIntConstant().value & REG_MASK;
int op3 = MIR_RotateAndMask.getMaskBegin(p).value & REG_MASK;
int op4 = MIR_RotateAndMask.getMaskEnd(p).value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6) | (op4 << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_RLWNM_opcode:
case PPC_RLWNMr_opcode:
{
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
int op2 = MIR_RotateAndMask.getShift(p).asRegister().getRegister().number & REG_MASK;
int op3 = MIR_RotateAndMask.getMaskBegin(p).value & REG_MASK;
int op4 = MIR_RotateAndMask.getMaskEnd(p).value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6) | (op4 << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_B_opcode:
{
BranchOperand o = MIR_Branch.getTarget(p);
int targetOffset = resolveBranch(p, o.target, mi, mcOffsets);
machinecodes.set(mi++, inst | (targetOffset & LI_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_BLR_opcode:
case PPC_BCTR_opcode:
/* p , == bcctr 0x14,BI */
{
// INDIRECT BRANCH (Target == null)
machinecodes.set(mi++, inst);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_BC_opcode:
case PPC_BCOND_opcode:
/* p 38, BO == 001zy or 011zy */
case PPC_BCC_opcode:
/* p 38, BO == 0000y, 0001y, 0100y or 0101y */
{
// COND BRANCH
int op0 = MIR_CondBranch.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_CondBranch.getCond(p).value;
// Add (CR field)<<2 to make BI represent the correct
// condition bit (0..3) in the correct condition field (0..7).
// 1 <= op <= 7
int bo_bi = op0 << 2 | op1;
BranchOperand o = MIR_CondBranch.getTarget(p);
int targetOffset = resolveBranch(p, o.target, mi, mcOffsets);
if (targetOffset == 0) {
// unresolved branch
if (DEBUG)
VM.sysWriteln("**** Forward Cond. Branch ****");
machinecodes.set(mi++, inst | (bo_bi << 16));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
if (unsafeCondDispl) {
// assume we might need two words
// for now fill with NOP
machinecodes.set(mi++, NOPtemplate);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
}
} else if (targetOffset < MIN_COND_DISPL << 2) {
// one word is not enough
if (DEBUG)
VM.sysWriteln("**** Backward Long Cond. Branch ****");
// flip the condition and skip the following branch instruction
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
machinecodes.set(mi++, inst | flipCondition(bo_bi << 16) | (2 << 2));
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
// make a long branch to the target
machinecodes.set(mi++, Btemplate | ((targetOffset - 4) & LI_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
} else {
// one word is enough
if (DEBUG)
VM.sysWriteln("**** Backward Short Cond. Branch ****");
machinecodes.set(mi++, inst | (bo_bi << 16) | (targetOffset & BD_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
}
}
break;
case PPC_BCLR_opcode:
case PPC_BCCTR_opcode:
/* p , BO == 0z10y or 0z11y */
{
// INDIRECT COND BRANCH
int op0 = MIR_CondBranch.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_CondBranch.getCond(p).value;
// Add (CR field)<<2 to make BI represent the correct
// condition bit (0..3) in the correct condition field (0..7).
// 1 <= op <= 7
int bo_bi = op0 << 2 | op1;
machinecodes.set(mi++, inst | (bo_bi << 16));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWrite(disasm(machinecodes.get(mi - 1), 0));
}
break;
case PPC_BL_opcode:
case PPC_BL_SYS_opcode:
{
// CALL
BranchOperand o = MIR_Call.getTarget(p);
int targetOffset = resolveBranch(p, o.target, mi, mcOffsets);
machinecodes.set(mi++, inst | (targetOffset & LI_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_BLRL_opcode:
/* p 39, == bclrl 0x14,BI */
case PPC_BCTRL_opcode:
/* p , == bcctrl 0x14,BI */
case PPC_BCTRL_SYS_opcode:
/* p , == bcctrl 0x14,BI */
{
// INDIRECT CALL (Target == null)
machinecodes.set(mi++, inst);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_BCL_opcode:
{
// COND CALL
int op0 = MIR_CondCall.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_CondCall.getCond(p).value;
// Add (CR field)<<2 to make BI represent the correct
// condition bit (0..3) in the correct condition field (0..7).
// 1 <= op <= 7
int bo_bi = op0 << 2 | op1;
BranchOperand o = MIR_CondCall.getTarget(p);
int targetOffset = resolveBranch(p, o.target, mi, mcOffsets);
if (targetOffset == 0) {
// unresolved branch
if (DEBUG)
VM.sysWriteln("**** Forward Cond. Branch ****");
machinecodes.set(mi++, inst | (bo_bi << 16));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
if (unsafeCondDispl) {
// assume we need two words
// for now fill with NOP
machinecodes.set(mi++, NOPtemplate);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
}
} else if (targetOffset < MIN_COND_DISPL << 2) {
// one instruction is not enough
throw new OperationNotImplementedException(// --dave
"Support for long backwards conditional branch and link is incorrect.");
/*
-- we have to branch (and not link) around an
unconditional branch and link.
-- the code below generates a conditional branch and
link around an unconditional branch.
if (DEBUG) VM.sysWriteln("**** Backward Long Cond. Branch ****");
// flip the condition and skip the following branch instruction
machinecodes.set(mi++, inst | flipCondition(bo_bi<<16) | (2<<2));
if (DEBUG) printInstruction(mi-1, inst,
flipCondition(bo_bi<<16), 2<<2);
// make a long branch to the target
machinecodes.set(mi++, Btemplate | ((targetOffset-4) & LI_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG) printInstruction(mi-1, Btemplate, targetOffset-4);
*/
} else {
// one instruction is enough
if (DEBUG)
VM.sysWriteln("**** Backward Short Cond. Branch ****");
machinecodes.set(mi++, inst | (bo_bi << 16) | (targetOffset & BD_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWrite(disasm(machinecodes.get(mi - 1), 0));
}
}
break;
case PPC_BCLRL_opcode:
{
// INDIRECT COND CALL
int op0 = MIR_CondCall.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_CondCall.getCond(p).value;
// Add (CR field)<<2 to make BI represent the correct
// condition bit (0..3) in the correct condition field (0..7).
// 1 <= op <= 7
int bo_bi = op0 << 2 | op1;
machinecodes.set(mi++, inst | (bo_bi << 16));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWrite(disasm(machinecodes.get(mi - 1), 0));
}
break;
case PPC_CMP_opcode:
case PPC_CMPL_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_CMP_opcode:
case PPC64_CMPL_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_CMPI_opcode:
case PPC_CMPLI_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_CMPI_opcode:
case PPC64_CMPLI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FMR_opcode:
{
int op0 = MIR_Move.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Move.getValue(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FABS_opcode:
case PPC_FNEG_opcode:
case PPC_FSQRT_opcode:
case PPC_FSQRTS_opcode:
case PPC_FRSP_opcode:
case PPC_FCTIW_opcode:
case PPC_FCTIWZ_opcode:
{
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_FCFID_opcode:
case PPC64_FCTIDZ_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FCMPO_opcode:
case PPC_FCMPU_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FMUL_opcode:
case PPC_FMULS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 6)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FMADD_opcode:
case PPC_FMADDS_opcode:
case PPC_FMSUB_opcode:
case PPC_FMSUBS_opcode:
case PPC_FNMADD_opcode:
case PPC_FNMADDS_opcode:
case PPC_FNMSUB_opcode:
case PPC_FNMSUBS_opcode:
case PPC_FSEL_opcode:
{
int op0 = MIR_Ternary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Ternary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Ternary.getValue2(p).getRegister().number & REG_MASK;
int op3 = MIR_Ternary.getValue3(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 6) | (op3 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LWZ_opcode:
case PPC_LBZ_opcode:
case PPC_LHA_opcode:
case PPC_LHZ_opcode:
case PPC_LFD_opcode:
case PPC_LFS_opcode:
case PPC_LMW_opcode:
{
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Load.getOffset(p).asIntConstant().value & SHORT_MASK;
int op2 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1 | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_LD_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = (MIR_Load.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LAddr_opcode:
case PPC_LInt_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Load.getOffset(p).asIntConstant().value & SHORT_MASK;
int op2 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1 | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = (MIR_Load.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC_STW_opcode:
case PPC_STB_opcode:
case PPC_STH_opcode:
case PPC_STFD_opcode:
case PPC_STFS_opcode:
case PPC_STMW_opcode:
{
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_Store.getOffset(p).asIntConstant().value & SHORT_MASK;
int op2 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1 | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_STWU_opcode:
case PPC_STFDU_opcode:
case PPC_STFSU_opcode:
{
int op0 = MIR_StoreUpdate.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_StoreUpdate.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_StoreUpdate.getOffset(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_STD_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = (MIR_Store.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_STAddr_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_Store.getOffset(p).asIntConstant().value & SHORT_MASK;
int op2 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1 | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = (MIR_Store.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC_STAddrU_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_StoreUpdate.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_StoreUpdate.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_StoreUpdate.getOffset(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_StoreUpdate.getValue(p).getRegister().number & REG_MASK;
int op1 = (MIR_StoreUpdate.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_StoreUpdate.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC_MFSPR_opcode:
{
int op0 = MIR_Move.getResult(p).getRegister().number & REG_MASK;
int op1 = phys.getSPR(MIR_Move.getValue(p).getRegister());
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_MTSPR_opcode:
{
int op0 = phys.getSPR(MIR_Move.getResult(p).getRegister());
int op1 = MIR_Move.getValue(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_MFTB_opcode:
case PPC_MFTBU_opcode:
{
int op0 = MIR_Move.getResult(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_HWSYNC_opcode:
case PPC_SYNC_opcode:
case PPC_ISYNC_opcode:
{
machinecodes.set(mi++, inst);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_DCBST_opcode:
case PPC_DCBT_opcode:
case PPC_DCBTST_opcode:
case PPC_DCBZ_opcode:
case PPC_DCBZL_opcode:
case PPC_DCBF_opcode:
case PPC_ICBI_opcode:
{
int op0 = MIR_CacheOp.getAddress(p).getRegister().number & REG_MASK;
int op1 = MIR_CacheOp.getOffset(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_ILLEGAL_INSTRUCTION_opcode:
{
machinecodes.set(mi++, inst);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case IG_PATCH_POINT_opcode:
{
BranchOperand bop = InlineGuard.getTarget(p);
Instruction target = bop.target;
if (VM.VerifyAssertions) {
VM._assert(target.getOpcode() == LABEL_opcode);
}
// resolve the target instruction, in LABEL_opcode,
// add one case for IG_PATCH_POINT
/* int targetOffset = */
resolveBranch(p, target, mi, mcOffsets);
machinecodes.set(mi++, NOPtemplate);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG_CODE_PATCH) {
VM.sysWrite("to be patched at ", mi - 1);
VM.sysWrite(" inst ");
VM.sysWriteHex(machinecodes.get(mi - 1));
VM.sysWriteln();
}
}
break;
default:
throw new OptimizingCompilerException("CodeGen", "OPCODE not implemented:", p);
}
}
if (unresolvedBranches != 0) {
throw new OptimizingCompilerException("CodeGen", " !!! Unresolved Branch Targets Exist!!! \n");
}
if (shouldPrint) {
OptimizingCompiler.header("Final machine code", ir.method);
Lister lister = new Lister(null);
lister.addLinesForCode(machinecodes);
lister.endAndPrintListing();
}
return mi;
}
Also used :
CodeArray(org.jikesrvm.compilers.common.CodeArray)
Lister(org.jikesrvm.compilers.common.assembler.ppc.Lister)
PhysicalRegisterSet(org.jikesrvm.compilers.opt.ir.ppc.PhysicalRegisterSet)
MachineCodeOffsets(org.jikesrvm.compilers.opt.mir2mc.MachineCodeOffsets)
OptimizingCompilerException(org.jikesrvm.compilers.opt.OptimizingCompilerException)
Instruction(org.jikesrvm.compilers.opt.ir.Instruction)
OperationNotImplementedException(org.jikesrvm.compilers.opt.OperationNotImplementedException)
BranchOperand(org.jikesrvm.compilers.opt.ir.operand.BranchOperand)
Example 2 with OperationNotImplementedException
use of org.jikesrvm.compilers.opt.OperationNotImplementedException in project JikesRVM by JikesRVM.
the class Dominators method perform.
/**
* Calculate the dominators for an IR.
*
* @param ir the IR in question
*/
public void perform(IR ir) {
if (ir.hasReachableExceptionHandlers()) {
throw new OperationNotImplementedException("IR with exception handlers");
}
DominatorSystem system = new DominatorSystem(ir);
if (DEBUG) {
System.out.print("Solving...");
}
if (DEBUG) {
System.out.println(system);
}
system.solve();
if (DEBUG) {
System.out.println("done");
}
DF_Solution solution = system.getSolution();
if (DEBUG) {
System.out.println("Dominator Solution :" + solution);
}
if (DEBUG) {
System.out.print("Updating blocks ...");
}
updateBlocks(solution);
if (DEBUG) {
System.out.println("done.");
}
if (ir.options.PRINT_DOMINATORS) {
printDominators(ir);
}
}
Also used :
DF_Solution(org.jikesrvm.compilers.opt.dfsolver.DF_Solution)
OperationNotImplementedException(org.jikesrvm.compilers.opt.OperationNotImplementedException)
Aggregations
OperationNotImplementedException (org.jikesrvm.compilers.opt.OperationNotImplementedException)2
CodeArray (org.jikesrvm.compilers.common.CodeArray)1
Lister (org.jikesrvm.compilers.common.assembler.ppc.Lister)1
OptimizingCompilerException (org.jikesrvm.compilers.opt.OptimizingCompilerException)1
DF_Solution (org.jikesrvm.compilers.opt.dfsolver.DF_Solution)1
Instruction (org.jikesrvm.compilers.opt.ir.Instruction)1
BranchOperand (org.jikesrvm.compilers.opt.ir.operand.BranchOperand)1
PhysicalRegisterSet (org.jikesrvm.compilers.opt.ir.ppc.PhysicalRegisterSet)1
MachineCodeOffsets (org.jikesrvm.compilers.opt.mir2mc.MachineCodeOffsets)1
