Example 1 with OptimizingCompilerException
use of org.jikesrvm.compilers.opt.OptimizingCompilerException in project JikesRVM by JikesRVM.
the class DynamicCallGraphOrganizer method thresholdReached.
/**
* Process contents of buffer:
* add call graph edges and increment their weights.
*/
@Override
void thresholdReached() {
if (DEBUG)
VM.sysWriteln("DCG_Organizer.thresholdReached()");
for (int i = 0; i < bufferSize; i = i + 3) {
int calleeCMID = 0;
// FIXME: This is necessary but hacky and may not even be correct.
while (calleeCMID == 0) {
calleeCMID = buffer[i + 0];
}
CompiledMethod compiledMethod = CompiledMethods.getCompiledMethod(calleeCMID);
if (compiledMethod == null)
continue;
RVMMethod callee = compiledMethod.getMethod();
if (callee.isRuntimeServiceMethod()) {
if (DEBUG)
VM.sysWrite("Skipping sample with runtime service callee");
continue;
}
int callerCMID = buffer[i + 1];
compiledMethod = CompiledMethods.getCompiledMethod(callerCMID);
if (compiledMethod == null)
continue;
RVMMethod stackFrameCaller = compiledMethod.getMethod();
int MCOff = buffer[i + 2];
Offset MCOffset = Offset.fromIntSignExtend(buffer[i + 2]);
int bytecodeIndex = -1;
RVMMethod caller = null;
switch(compiledMethod.getCompilerType()) {
case CompiledMethod.TRAP:
case CompiledMethod.JNI:
if (DEBUG)
VM.sysWrite("Skipping sample with TRAP/JNI caller");
continue;
case CompiledMethod.BASELINE:
{
BaselineCompiledMethod baseCompiledMethod = (BaselineCompiledMethod) compiledMethod;
// note: the following call expects the offset in INSTRUCTIONS!
bytecodeIndex = baseCompiledMethod.findBytecodeIndexForInstruction(MCOffset);
caller = stackFrameCaller;
}
break;
case CompiledMethod.OPT:
{
OptCompiledMethod optCompiledMethod = (OptCompiledMethod) compiledMethod;
OptMachineCodeMap mc_map = optCompiledMethod.getMCMap();
try {
bytecodeIndex = mc_map.getBytecodeIndexForMCOffset(MCOffset);
if (bytecodeIndex == -1) {
// so skip the sample.
if (DEBUG) {
VM.sysWrite(" *** SKIP SAMPLE ", stackFrameCaller.toString());
VM.sysWrite("@", compiledMethod.toString());
VM.sysWrite(" at MC offset ", MCOff);
VM.sysWrite(" calling ", callee.toString());
VM.sysWriteln(" due to invalid bytecodeIndex");
}
// skip sample.
continue;
}
} catch (java.lang.ArrayIndexOutOfBoundsException e) {
VM.sysWrite(" ***ERROR: getBytecodeIndexForMCOffset(", MCOffset);
VM.sysWriteln(") ArrayIndexOutOfBounds!");
e.printStackTrace();
if (VM.ErrorsFatal)
VM.sysFail("Exception in AI organizer.");
caller = stackFrameCaller;
// skip sample
continue;
} catch (OptimizingCompilerException e) {
VM.sysWrite("***Error: SKIP SAMPLE: can't find bytecode index in OPT compiled " + stackFrameCaller + "@" + compiledMethod + " at MC offset ", MCOff);
VM.sysWriteln("!");
if (VM.ErrorsFatal)
VM.sysFail("Exception in AI organizer.");
// skip sample
continue;
}
try {
caller = mc_map.getMethodForMCOffset(MCOffset);
} catch (java.lang.ArrayIndexOutOfBoundsException e) {
VM.sysWrite(" ***ERROR: getMethodForMCOffset(", MCOffset);
VM.sysWriteln(") ArrayIndexOutOfBounds!");
e.printStackTrace();
if (VM.ErrorsFatal)
VM.sysFail("Exception in AI organizer.");
caller = stackFrameCaller;
continue;
} catch (OptimizingCompilerException e) {
VM.sysWrite("***Error: SKIP SAMPLE: can't find caller in OPT compiled " + stackFrameCaller + "@" + compiledMethod + " at MC offset ", MCOff);
VM.sysWriteln("!");
if (VM.ErrorsFatal)
VM.sysFail("Exception in AI organizer.");
// skip sample
continue;
}
if (caller == null) {
VM.sysWrite(" ***ERROR: getMethodForMCOffset(", MCOffset);
VM.sysWriteln(") returned null!");
caller = stackFrameCaller;
// skip sample
continue;
}
}
break;
}
// increment the call graph edge, adding it if needed
Controller.dcg.incrementEdge(caller, bytecodeIndex, callee);
}
if (thresholdReachedCount > 0) {
thresholdReachedCount--;
}
}
Also used :
RVMMethod(org.jikesrvm.classloader.RVMMethod)
OptCompiledMethod(org.jikesrvm.compilers.opt.runtimesupport.OptCompiledMethod)
OptMachineCodeMap(org.jikesrvm.compilers.opt.runtimesupport.OptMachineCodeMap)
BaselineCompiledMethod(org.jikesrvm.compilers.baseline.BaselineCompiledMethod)
OptimizingCompilerException(org.jikesrvm.compilers.opt.OptimizingCompilerException)
BaselineCompiledMethod(org.jikesrvm.compilers.baseline.BaselineCompiledMethod)
CompiledMethod(org.jikesrvm.compilers.common.CompiledMethod)
OptCompiledMethod(org.jikesrvm.compilers.opt.runtimesupport.OptCompiledMethod)
Offset(org.vmmagic.unboxed.Offset)
Example 2 with OptimizingCompilerException
use of org.jikesrvm.compilers.opt.OptimizingCompilerException in project JikesRVM by JikesRVM.
the class AssemblerOpt method backpatchForwardBranches.
/**
* Back-patches any forward branches to the given instruction.
* <p>
* Note: The updated index into the machine code array would normally need
* to be returned but this method currently does not modify the index.
*
* @param branchTarget the LABEL instruction to process
* @param machinecodes machine code array
* @param machineCodeIndex current index into the machine code array
* @param mcOffsets machine code offsets
*/
private void backpatchForwardBranches(Instruction branchTarget, CodeArray machinecodes, int machineCodeIndex, MachineCodeOffsets mcOffsets) {
Iterator<Instruction> branchSources = branchBackPatching.getBranchSources(branchTarget);
while (branchSources.hasNext()) {
Instruction branchStmt = branchSources.next();
int bo = mcOffsets.getMachineCodeOffset(branchStmt) - (1 << LG_INSTRUCTION_WIDTH);
int bi = bo >> LG_INSTRUCTION_WIDTH;
int targetOffset = (machineCodeIndex - bi) << LG_INSTRUCTION_WIDTH;
boolean setLink = false;
if (targetOffset > MAX_DISPL << LG_INSTRUCTION_WIDTH) {
throw new OptimizingCompilerException("CodeGen", "Branch positive offset too large: ", targetOffset);
}
switch(branchStmt.getOpcode()) {
case PPC_B_opcode:
case PPC_BL_opcode:
machinecodes.set(bi, machinecodes.get(bi) | targetOffset & LI_MASK);
break;
case PPC_DATA_LABEL_opcode:
machinecodes.set(bi, targetOffset);
break;
// of target offset, and will fail if it is out of range
case IG_PATCH_POINT_opcode:
// do nothing
break;
case PPC_BCL_opcode:
setLink = true;
// fall through!
default:
// conditional branches
if (targetOffset <= MAX_COND_DISPL << 2) {
// one word is enough
machinecodes.set(bi, machinecodes.get(bi) | targetOffset & BD_MASK);
if (DEBUG) {
VM.sysWriteln("**** Forward Short Cond. Branch ****");
VM.sysWriteln(disasm(machinecodes.get(bi), 0));
}
} else {
// one word is not enough
// we're moving the "real" branch ahead 1 instruction
// if it's a GC point (eg BCL for yieldpoint) then we must
// make sure the GCMap is generated at the correct mc offset.
int oldOffset = mcOffsets.getMachineCodeOffset(branchStmt);
mcOffsets.setMachineCodeOffset(branchStmt, oldOffset + (1 << LG_INSTRUCTION_WIDTH));
// flip the condition and skip the next branch instruction
machinecodes.set(bi, flipCondition(machinecodes.get(bi)));
machinecodes.set(bi, machinecodes.get(bi) | (2 << LG_INSTRUCTION_WIDTH));
// turn off link bit.
machinecodes.set(bi, machinecodes.get(bi) & 0xfffffffe);
// make a long branch
machinecodes.set(bi + 1, Btemplate | ((targetOffset - 4) & LI_MASK));
if (setLink) {
// turn on link bit.
machinecodes.set(bi + 1, machinecodes.get(bi + 1) | 1);
}
if (DEBUG) {
VM.sysWriteln("**** Forward Long Cond. Branch ****");
VM.sysWriteln(disasm(machinecodes.get(bi), 0));
VM.sysWriteln(disasm(machinecodes.get(bi + 1), 0));
}
}
break;
}
unresolvedBranches--;
}
mcOffsets.setMachineCodeOffset(branchTarget, machineCodeIndex << LG_INSTRUCTION_WIDTH);
}
Also used :
OptimizingCompilerException(org.jikesrvm.compilers.opt.OptimizingCompilerException)
Instruction(org.jikesrvm.compilers.opt.ir.Instruction)
Example 3 with OptimizingCompilerException
use of org.jikesrvm.compilers.opt.OptimizingCompilerException in project JikesRVM by JikesRVM.
the class AssemblerOpt method genCode.
protected final int genCode(IR ir, boolean shouldPrint) {
int mi = 0;
CodeArray machinecodes = ir.MIRInfo.machinecode;
PhysicalRegisterSet phys = ir.regpool.getPhysicalRegisterSet().asPPC();
int labelCountEstimate = ir.cfg.numberOfNodes();
branchBackPatching = new BranchInformationForBackPatching(labelCountEstimate);
boolean unsafeCondDispl = machinecodes.length() > MAX_COND_DISPL;
// boolean unsafeDispl = machinecodes.length() > MAX_DISPL;
MachineCodeOffsets mcOffsets = ir.MIRInfo.mcOffsets;
for (Instruction p = ir.firstInstructionInCodeOrder(); p != null; p = p.nextInstructionInCodeOrder()) {
int inst = p.operator().instTemplate();
switch(p.getOpcode()) {
case LABEL_opcode:
backpatchForwardBranches(p, machinecodes, mi, mcOffsets);
break;
case BBEND_opcode:
case UNINT_BEGIN_opcode:
case UNINT_END_opcode:
case GUARD_MOVE_opcode:
case GUARD_COMBINE_opcode:
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
break;
case PPC_DATA_INT_opcode:
{
int value = MIR_DataInt.getValue(p).value;
machinecodes.set(mi++, value);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_DATA_LABEL_opcode:
{
Instruction target = MIR_DataLabel.getTarget(p).target;
int targetOffset = resolveBranch(p, target, mi, mcOffsets);
machinecodes.set(mi++, targetOffset);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_CRAND_opcode:
case PPC_CRANDC_opcode:
case PPC_CROR_opcode:
case PPC_CRORC_opcode:
{
int op0 = MIR_Condition.getResultBit(p).value & REG_MASK;
int op1 = MIR_Condition.getValue1Bit(p).value & REG_MASK;
int op2 = MIR_Condition.getValue2Bit(p).value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_ADD_opcode:
case PPC_ADDr_opcode:
case PPC_ADDC_opcode:
case PPC_ADDE_opcode:
case PPC_SUBF_opcode:
case PPC_SUBFr_opcode:
case PPC_SUBFC_opcode:
case PPC_SUBFCr_opcode:
case PPC_SUBFE_opcode:
case PPC_FADD_opcode:
case PPC_FADDS_opcode:
case PPC_FDIV_opcode:
case PPC_FDIVS_opcode:
case PPC_DIVW_opcode:
case PPC_DIVWU_opcode:
case PPC_MULLW_opcode:
case PPC_MULHW_opcode:
case PPC_MULHWU_opcode:
case PPC_FSUB_opcode:
case PPC_FSUBS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_MULLD_opcode:
case PPC64_DIVD_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LWZX_opcode:
case PPC_LWARX_opcode:
case PPC_LBZX_opcode:
case PPC_LHAX_opcode:
case PPC_LHZX_opcode:
case PPC_LFDX_opcode:
case PPC_LFSX_opcode:
case PPC_LIntX_opcode:
case PPC_LAddrARX_opcode:
case PPC_LAddrX_opcode:
{
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_Load.getOffset(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_LDX_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_Load.getOffset(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_STWX_opcode:
case PPC_STWCXr_opcode:
case PPC_STBX_opcode:
case PPC_STHX_opcode:
case PPC_STFDX_opcode:
case PPC_STFSX_opcode:
case PPC_STAddrCXr_opcode:
case PPC_STAddrX_opcode:
case PPC_STAddrUX_opcode:
{
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_Store.getOffset(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LWZUX_opcode:
case PPC_LBZUX_opcode:
case PPC_LIntUX_opcode:
case PPC_LAddrUX_opcode:
{
int op0 = MIR_LoadUpdate.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_LoadUpdate.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_LoadUpdate.getOffset(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LWZU_opcode:
{
int op0 = MIR_LoadUpdate.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_LoadUpdate.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_LoadUpdate.getOffset(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_TW_opcode:
case PPC_TAddr_opcode:
{
int op0 = MIR_Trap.getCond(p).value;
int op1 = MIR_Trap.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Trap.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_TD_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Trap.getCond(p).value;
int op1 = MIR_Trap.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Trap.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_TWI_opcode:
{
int op0 = MIR_Trap.getCond(p).value;
int op1 = MIR_Trap.getValue1(p).getRegister().number & REG_MASK;
int op2;
if (VM.BuildFor64Addr && MIR_Trap.getValue2(p).isLongConstant()) {
op2 = ((int) MIR_Trap.getValue2(p).asLongConstant().value) & SHORT_MASK;
} else {
op2 = MIR_Trap.getValue2(p).asIntConstant().value & SHORT_MASK;
}
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_TDI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Trap.getCond(p).value;
int op1 = MIR_Trap.getValue1(p).getRegister().number & REG_MASK;
int op2;
if (MIR_Trap.getValue2(p).isLongConstant()) {
op2 = ((int) MIR_Trap.getValue2(p).asLongConstant().value) & SHORT_MASK;
} else {
op2 = MIR_Trap.getValue2(p).asIntConstant().value & SHORT_MASK;
}
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case NULL_CHECK_opcode:
/* Just a nicer name for a twi <ref> lessthan 1 */
{
int op0 = PowerPCTrapOperand.LOWER;
int op1 = ((RegisterOperand) NullCheck.getRef(p)).getRegister().number & REG_MASK;
int op2 = 1;
inst = VM.BuildFor64Addr ? PPC64_TDI.instTemplate() : PPC_TWI.instTemplate();
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LDI_opcode:
case PPC_LDIS_opcode:
// D_Form. pseudo instructions derived from PPC_ADDI and PPC_ADDIS
{
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_ADDIC_opcode:
case PPC_ADDICr_opcode:
case PPC_SUBFIC_opcode:
case PPC_MULLI_opcode:
case PPC_ADDI_opcode:
case PPC_ADDIS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_CNTLZW_opcode:
case PPC_CNTLZAddr_opcode:
case PPC_EXTSB_opcode:
case PPC_EXTSBr_opcode:
case PPC_EXTSH_opcode:
case PPC_EXTSHr_opcode:
{
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_EXTSW_opcode:
case PPC64_EXTSWr_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_EXTZW_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
// op3low = 0, so op3 == 32
int op3high = 1;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_ADDZE_opcode:
case PPC_SUBFZE_opcode:
case PPC_NEG_opcode:
case PPC_NEGr_opcode:
case PPC_ADDME_opcode:
{
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
// Bit positions of op1 and op2 are reversed.
case PPC_XORI_opcode:
case PPC_XORIS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
// Bit positions of op1 and op2 are reversed.
case PPC_AND_opcode:
case PPC_ANDr_opcode:
case PPC_NAND_opcode:
case PPC_NANDr_opcode:
case PPC_ANDC_opcode:
case PPC_ANDCr_opcode:
case PPC_OR_opcode:
case PPC_ORr_opcode:
case PPC_NOR_opcode:
case PPC_NORr_opcode:
case PPC_ORC_opcode:
case PPC_ORCr_opcode:
case PPC_XOR_opcode:
case PPC_XORr_opcode:
case PPC_EQV_opcode:
case PPC_EQVr_opcode:
case PPC_SLW_opcode:
case PPC_SLWr_opcode:
case PPC_SRW_opcode:
case PPC_SRWr_opcode:
case PPC_SRAW_opcode:
case PPC_SRAWr_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_SLD_opcode:
case PPC64_SLDr_opcode:
case PPC64_SRD_opcode:
case PPC64_SRDr_opcode:
case PPC64_SRAD_opcode:
case PPC64_SRADr_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_MOVE_opcode:
/* pseudo opcode, equal to PPC_ORI with 0 */
{
int op0 = MIR_Move.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Move.getValue(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_SRWI_opcode:
/* pseudo opcode, equal to rlwinm Rx,Ry,32-n,n,31 */
case PPC_SRWIr_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int shift = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
int op2 = (32 - shift);
int op3 = shift;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
// Bit positions of op1 and op2 are reversed.
case PPC_SLWI_opcode:
case PPC_SLWIr_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int shift = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
int op2 = shift;
int op3 = (31 - shift);
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_SRAWI_opcode:
case PPC_SRAWIr_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_SRAddrI_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int shift = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
int op2 = (32 - shift);
int op3 = shift;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op3 = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2 = 64 - op3;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC_SRAAddrI_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC64_SRADI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_SRDI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op3 = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2 = 64 - op3;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case // shorthand via RLDICR
PPC64_SLDI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int shift = MIR_Binary.getValue2(p).asIntConstant().value & SIXBIT_MASK;
int op2 = shift;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
int op3 = 63 - shift;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_RLDICR_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
// shift
int op2 = MIR_RotateAndMask.getShift(p).asIntConstant().value & SIXBIT_MASK;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
// mask
int op3 = MIR_RotateAndMask.getMaskEnd(p).value & SIXBIT_MASK;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
if (VM.VerifyAssertions) {
int op4 = MIR_RotateAndMask.getMaskBegin(p).value & SIXBIT_MASK;
VM._assert(op4 == 0);
}
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_RLDICL_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
// shift
int op2 = MIR_RotateAndMask.getShift(p).asIntConstant().value & SIXBIT_MASK;
int op2low = op2 & 0x1F;
int op2high = (op2 & 0x20) >>> 5;
// mask
int op3 = MIR_RotateAndMask.getMaskBegin(p).value & SIXBIT_MASK;
int op3low = op3 & 0x1F;
int op3high = (op3 & 0x20) >>> 5;
if (VM.VerifyAssertions) {
int op4 = MIR_RotateAndMask.getMaskEnd(p).value & SIXBIT_MASK;
VM._assert(op4 == 63);
}
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2low << 11) | (op2high << 1) | (op3low << 6) | (op3high << 5)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
// Bit positions of op1 and op2 are reversed.
case PPC_ANDIr_opcode:
case PPC_ANDISr_opcode:
case PPC_ORI_opcode:
case PPC_ORIS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_RLWINM_opcode:
case PPC_RLWINMr_opcode:
{
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
int op2 = MIR_RotateAndMask.getShift(p).asIntConstant().value & REG_MASK;
int op3 = MIR_RotateAndMask.getMaskBegin(p).value & REG_MASK;
int op4 = MIR_RotateAndMask.getMaskEnd(p).value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6) | (op4 << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_RLWIMI_opcode:
case PPC_RLWIMIr_opcode:
{
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op0f = MIR_RotateAndMask.getSource(p).getRegister().number & REG_MASK;
if (op0 != op0f) {
throw new OptimizingCompilerException("CodeGen", "format for RLWIMI is incorrect");
}
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
int op2 = MIR_RotateAndMask.getShift(p).asIntConstant().value & REG_MASK;
int op3 = MIR_RotateAndMask.getMaskBegin(p).value & REG_MASK;
int op4 = MIR_RotateAndMask.getMaskEnd(p).value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6) | (op4 << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_RLWNM_opcode:
case PPC_RLWNMr_opcode:
{
int op0 = MIR_RotateAndMask.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_RotateAndMask.getValue(p).getRegister().number & REG_MASK;
int op2 = MIR_RotateAndMask.getShift(p).asRegister().getRegister().number & REG_MASK;
int op3 = MIR_RotateAndMask.getMaskBegin(p).value & REG_MASK;
int op4 = MIR_RotateAndMask.getMaskEnd(p).value & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21) | (op2 << 11) | (op3 << 6) | (op4 << 1)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_B_opcode:
{
BranchOperand o = MIR_Branch.getTarget(p);
int targetOffset = resolveBranch(p, o.target, mi, mcOffsets);
machinecodes.set(mi++, inst | (targetOffset & LI_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_BLR_opcode:
case PPC_BCTR_opcode:
/* p , == bcctr 0x14,BI */
{
// INDIRECT BRANCH (Target == null)
machinecodes.set(mi++, inst);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_BC_opcode:
case PPC_BCOND_opcode:
/* p 38, BO == 001zy or 011zy */
case PPC_BCC_opcode:
/* p 38, BO == 0000y, 0001y, 0100y or 0101y */
{
// COND BRANCH
int op0 = MIR_CondBranch.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_CondBranch.getCond(p).value;
// Add (CR field)<<2 to make BI represent the correct
// condition bit (0..3) in the correct condition field (0..7).
// 1 <= op <= 7
int bo_bi = op0 << 2 | op1;
BranchOperand o = MIR_CondBranch.getTarget(p);
int targetOffset = resolveBranch(p, o.target, mi, mcOffsets);
if (targetOffset == 0) {
// unresolved branch
if (DEBUG)
VM.sysWriteln("**** Forward Cond. Branch ****");
machinecodes.set(mi++, inst | (bo_bi << 16));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
if (unsafeCondDispl) {
// assume we might need two words
// for now fill with NOP
machinecodes.set(mi++, NOPtemplate);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
}
} else if (targetOffset < MIN_COND_DISPL << 2) {
// one word is not enough
if (DEBUG)
VM.sysWriteln("**** Backward Long Cond. Branch ****");
// flip the condition and skip the following branch instruction
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
machinecodes.set(mi++, inst | flipCondition(bo_bi << 16) | (2 << 2));
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
// make a long branch to the target
machinecodes.set(mi++, Btemplate | ((targetOffset - 4) & LI_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
} else {
// one word is enough
if (DEBUG)
VM.sysWriteln("**** Backward Short Cond. Branch ****");
machinecodes.set(mi++, inst | (bo_bi << 16) | (targetOffset & BD_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
}
}
break;
case PPC_BCLR_opcode:
case PPC_BCCTR_opcode:
/* p , BO == 0z10y or 0z11y */
{
// INDIRECT COND BRANCH
int op0 = MIR_CondBranch.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_CondBranch.getCond(p).value;
// Add (CR field)<<2 to make BI represent the correct
// condition bit (0..3) in the correct condition field (0..7).
// 1 <= op <= 7
int bo_bi = op0 << 2 | op1;
machinecodes.set(mi++, inst | (bo_bi << 16));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWrite(disasm(machinecodes.get(mi - 1), 0));
}
break;
case PPC_BL_opcode:
case PPC_BL_SYS_opcode:
{
// CALL
BranchOperand o = MIR_Call.getTarget(p);
int targetOffset = resolveBranch(p, o.target, mi, mcOffsets);
machinecodes.set(mi++, inst | (targetOffset & LI_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_BLRL_opcode:
/* p 39, == bclrl 0x14,BI */
case PPC_BCTRL_opcode:
/* p , == bcctrl 0x14,BI */
case PPC_BCTRL_SYS_opcode:
/* p , == bcctrl 0x14,BI */
{
// INDIRECT CALL (Target == null)
machinecodes.set(mi++, inst);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_BCL_opcode:
{
// COND CALL
int op0 = MIR_CondCall.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_CondCall.getCond(p).value;
// Add (CR field)<<2 to make BI represent the correct
// condition bit (0..3) in the correct condition field (0..7).
// 1 <= op <= 7
int bo_bi = op0 << 2 | op1;
BranchOperand o = MIR_CondCall.getTarget(p);
int targetOffset = resolveBranch(p, o.target, mi, mcOffsets);
if (targetOffset == 0) {
// unresolved branch
if (DEBUG)
VM.sysWriteln("**** Forward Cond. Branch ****");
machinecodes.set(mi++, inst | (bo_bi << 16));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
if (unsafeCondDispl) {
// assume we need two words
// for now fill with NOP
machinecodes.set(mi++, NOPtemplate);
if (DEBUG)
VM.sysWriteln(disasm(machinecodes.get(mi - 1), 0));
}
} else if (targetOffset < MIN_COND_DISPL << 2) {
// one instruction is not enough
throw new OperationNotImplementedException(// --dave
"Support for long backwards conditional branch and link is incorrect.");
/*
-- we have to branch (and not link) around an
unconditional branch and link.
-- the code below generates a conditional branch and
link around an unconditional branch.
if (DEBUG) VM.sysWriteln("**** Backward Long Cond. Branch ****");
// flip the condition and skip the following branch instruction
machinecodes.set(mi++, inst | flipCondition(bo_bi<<16) | (2<<2));
if (DEBUG) printInstruction(mi-1, inst,
flipCondition(bo_bi<<16), 2<<2);
// make a long branch to the target
machinecodes.set(mi++, Btemplate | ((targetOffset-4) & LI_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG) printInstruction(mi-1, Btemplate, targetOffset-4);
*/
} else {
// one instruction is enough
if (DEBUG)
VM.sysWriteln("**** Backward Short Cond. Branch ****");
machinecodes.set(mi++, inst | (bo_bi << 16) | (targetOffset & BD_MASK));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWrite(disasm(machinecodes.get(mi - 1), 0));
}
}
break;
case PPC_BCLRL_opcode:
{
// INDIRECT COND CALL
int op0 = MIR_CondCall.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_CondCall.getCond(p).value;
// Add (CR field)<<2 to make BI represent the correct
// condition bit (0..3) in the correct condition field (0..7).
// 1 <= op <= 7
int bo_bi = op0 << 2 | op1;
machinecodes.set(mi++, inst | (bo_bi << 16));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG)
VM.sysWrite(disasm(machinecodes.get(mi - 1), 0));
}
break;
case PPC_CMP_opcode:
case PPC_CMPL_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_CMP_opcode:
case PPC64_CMPL_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_CMPI_opcode:
case PPC_CMPLI_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_CMPI_opcode:
case PPC64_CMPLI_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FMR_opcode:
{
int op0 = MIR_Move.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Move.getValue(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FABS_opcode:
case PPC_FNEG_opcode:
case PPC_FSQRT_opcode:
case PPC_FSQRTS_opcode:
case PPC_FRSP_opcode:
case PPC_FCTIW_opcode:
case PPC_FCTIWZ_opcode:
{
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_FCFID_opcode:
case PPC64_FCTIDZ_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Unary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Unary.getValue(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FCMPO_opcode:
case PPC_FCMPU_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 23) | (op1 << 16) | (op2 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FMUL_opcode:
case PPC_FMULS_opcode:
{
int op0 = MIR_Binary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Binary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Binary.getValue2(p).asRegister().getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 6)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_FMADD_opcode:
case PPC_FMADDS_opcode:
case PPC_FMSUB_opcode:
case PPC_FMSUBS_opcode:
case PPC_FNMADD_opcode:
case PPC_FNMADDS_opcode:
case PPC_FNMSUB_opcode:
case PPC_FNMSUBS_opcode:
case PPC_FSEL_opcode:
{
int op0 = MIR_Ternary.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Ternary.getValue1(p).getRegister().number & REG_MASK;
int op2 = MIR_Ternary.getValue2(p).getRegister().number & REG_MASK;
int op3 = MIR_Ternary.getValue3(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | (op2 << 6) | (op3 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LWZ_opcode:
case PPC_LBZ_opcode:
case PPC_LHA_opcode:
case PPC_LHZ_opcode:
case PPC_LFD_opcode:
case PPC_LFS_opcode:
case PPC_LMW_opcode:
{
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Load.getOffset(p).asIntConstant().value & SHORT_MASK;
int op2 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1 | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_LD_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = (MIR_Load.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_LAddr_opcode:
case PPC_LInt_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = MIR_Load.getOffset(p).asIntConstant().value & SHORT_MASK;
int op2 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1 | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_Load.getResult(p).getRegister().number & REG_MASK;
int op1 = (MIR_Load.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_Load.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC_STW_opcode:
case PPC_STB_opcode:
case PPC_STH_opcode:
case PPC_STFD_opcode:
case PPC_STFS_opcode:
case PPC_STMW_opcode:
{
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_Store.getOffset(p).asIntConstant().value & SHORT_MASK;
int op2 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1 | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_STWU_opcode:
case PPC_STFDU_opcode:
case PPC_STFSU_opcode:
{
int op0 = MIR_StoreUpdate.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_StoreUpdate.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_StoreUpdate.getOffset(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC64_STD_opcode:
{
if (VM.VerifyAssertions)
VM._assert(VM.BuildFor64Addr);
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = (MIR_Store.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_STAddr_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_Store.getOffset(p).asIntConstant().value & SHORT_MASK;
int op2 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | op1 | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_Store.getValue(p).getRegister().number & REG_MASK;
int op1 = (MIR_Store.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_Store.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC_STAddrU_opcode:
{
if (VM.BuildFor32Addr) {
int op0 = MIR_StoreUpdate.getValue(p).getRegister().number & REG_MASK;
int op1 = MIR_StoreUpdate.getAddress(p).getRegister().number & REG_MASK;
int op2 = MIR_StoreUpdate.getOffset(p).asIntConstant().value & SHORT_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16) | op2));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
} else {
int op0 = MIR_StoreUpdate.getValue(p).getRegister().number & REG_MASK;
int op1 = (MIR_StoreUpdate.getOffset(p).asIntConstant().value >> 2) & SHORT14_MASK;
int op2 = MIR_StoreUpdate.getAddress(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 2) | (op2 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
}
break;
case PPC_MFSPR_opcode:
{
int op0 = MIR_Move.getResult(p).getRegister().number & REG_MASK;
int op1 = phys.getSPR(MIR_Move.getValue(p).getRegister());
machinecodes.set(mi++, (inst | (op0 << 21) | (op1 << 16)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_MTSPR_opcode:
{
int op0 = phys.getSPR(MIR_Move.getResult(p).getRegister());
int op1 = MIR_Move.getValue(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_MFTB_opcode:
case PPC_MFTBU_opcode:
{
int op0 = MIR_Move.getResult(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 21)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_HWSYNC_opcode:
case PPC_SYNC_opcode:
case PPC_ISYNC_opcode:
{
machinecodes.set(mi++, inst);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_DCBST_opcode:
case PPC_DCBT_opcode:
case PPC_DCBTST_opcode:
case PPC_DCBZ_opcode:
case PPC_DCBZL_opcode:
case PPC_DCBF_opcode:
case PPC_ICBI_opcode:
{
int op0 = MIR_CacheOp.getAddress(p).getRegister().number & REG_MASK;
int op1 = MIR_CacheOp.getOffset(p).getRegister().number & REG_MASK;
machinecodes.set(mi++, (inst | (op0 << 16) | (op1 << 11)));
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case PPC_ILLEGAL_INSTRUCTION_opcode:
{
machinecodes.set(mi++, inst);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
}
break;
case IG_PATCH_POINT_opcode:
{
BranchOperand bop = InlineGuard.getTarget(p);
Instruction target = bop.target;
if (VM.VerifyAssertions) {
VM._assert(target.getOpcode() == LABEL_opcode);
}
// resolve the target instruction, in LABEL_opcode,
// add one case for IG_PATCH_POINT
/* int targetOffset = */
resolveBranch(p, target, mi, mcOffsets);
machinecodes.set(mi++, NOPtemplate);
mcOffsets.setMachineCodeOffset(p, mi << LG_INSTRUCTION_WIDTH);
if (DEBUG_CODE_PATCH) {
VM.sysWrite("to be patched at ", mi - 1);
VM.sysWrite(" inst ");
VM.sysWriteHex(machinecodes.get(mi - 1));
VM.sysWriteln();
}
}
break;
default:
throw new OptimizingCompilerException("CodeGen", "OPCODE not implemented:", p);
}
}
if (unresolvedBranches != 0) {
throw new OptimizingCompilerException("CodeGen", " !!! Unresolved Branch Targets Exist!!! \n");
}
if (shouldPrint) {
OptimizingCompiler.header("Final machine code", ir.method);
Lister lister = new Lister(null);
lister.addLinesForCode(machinecodes);
lister.endAndPrintListing();
}
return mi;
}
Also used :
CodeArray(org.jikesrvm.compilers.common.CodeArray)
Lister(org.jikesrvm.compilers.common.assembler.ppc.Lister)
PhysicalRegisterSet(org.jikesrvm.compilers.opt.ir.ppc.PhysicalRegisterSet)
MachineCodeOffsets(org.jikesrvm.compilers.opt.mir2mc.MachineCodeOffsets)
OptimizingCompilerException(org.jikesrvm.compilers.opt.OptimizingCompilerException)
Instruction(org.jikesrvm.compilers.opt.ir.Instruction)
OperationNotImplementedException(org.jikesrvm.compilers.opt.OperationNotImplementedException)
BranchOperand(org.jikesrvm.compilers.opt.ir.operand.BranchOperand)
Example 4 with OptimizingCompilerException
use of org.jikesrvm.compilers.opt.OptimizingCompilerException in project JikesRVM by JikesRVM.
the class Inliner method execute.
/**
* Return a generation context that represents the
* execution of inlDec in the context <code><parent,ebag></code> for
* the call instruction callSite.
* <p> PRECONDITION: inlDec.isYes()
* <p> POSTCONDITIONS:
* Let gc be the returned generation context.
* <ul>
* <li> gc.cfg.firstInCodeOrder is the entry to the inlined context
* <li>gc.cfg.lastInCodeOrder is the exit from the inlined context
* <li> GenerationContext.transferState(parent, child) has been called.
* </ul>
*
* @param inlDec the inlining decision to execute
* @param parent the caller generation context
* @param ebag exception handler scope for the caller
* @param callSite the callsite to execute
* @return a generation context that represents the execution of the
* inline decision in the given context
*/
public static GenerationContext execute(InlineDecision inlDec, GenerationContext parent, ExceptionHandlerBasicBlockBag ebag, Instruction callSite) {
if (inlDec.needsGuard()) {
// Step 1: create the synthetic generation context we'll
// return to our caller.
GenerationContext container = GenerationContext.createSynthetic(parent, ebag);
container.getCfg().breakCodeOrder(container.getPrologue(), container.getEpilogue());
// Step 2: (a) Print a message (optional)
// (b) Generate the child GC for each target
RVMMethod[] targets = inlDec.getTargets();
byte[] guards = inlDec.getGuards();
GenerationContext[] children = new GenerationContext[targets.length];
for (int i = 0; i < targets.length; i++) {
NormalMethod callee = (NormalMethod) targets[i];
// (a)
if (parent.getOptions().PRINT_INLINE_REPORT) {
String guard = guards[i] == OptOptions.INLINE_GUARD_CLASS_TEST ? " (class test) " : " (method test) ";
VM.sysWriteln("\tGuarded inline" + guard + " " + callee + " into " + callSite.position().getMethod() + " at bytecode " + callSite.getBytecodeIndex());
}
// (b)
children[i] = parent.createChildContext(ebag, callee, callSite);
BC2IR.generateHIR(children[i]);
children[i].transferStateToParent();
}
// special purpose coding wrapping the calls to Operand.meet.
if (Call.hasResult(callSite)) {
Register reg = Call.getResult(callSite).getRegister();
container.setResult(children[0].getResult());
for (int i = 1; i < targets.length; i++) {
if (children[i].getResult() != null) {
container.setResult((container.getResult() == null) ? children[i].getResult() : Operand.meet(container.getResult(), children[i].getResult(), reg));
}
}
if (!inlDec.OSRTestFailed()) {
// Account for the non-predicted case as well...
RegisterOperand failureCaseResult = Call.getResult(callSite).copyRO();
container.setResult((container.getResult() == null) ? failureCaseResult : Operand.meet(container.getResult(), failureCaseResult, reg));
}
}
// Step 4: Create a block to contain a copy of the original call or an OSR_Yieldpoint
// to cover the case that all predictions fail.
BasicBlock testFailed = new BasicBlock(callSite.getBytecodeIndex(), callSite.position(), parent.getCfg());
testFailed.setExceptionHandlers(ebag);
if (COUNT_FAILED_GUARDS && Controller.options.INSERT_DEBUGGING_COUNTERS) {
// Get a dynamic count of how many times guards fail at runtime.
// Need a name for the event to count. In this example, a
// separate counter for each method by using the method name
// as the event name. You could also have used just the string
// "Guarded inline failed" to keep only one counter.
String eventName = "Guarded inline failed: " + callSite.position().getMethod().toString();
// Create instruction that will increment the counter
// corresponding to the named event.
Instruction counterInst = AOSDatabase.debuggingCounterData.getCounterInstructionForEvent(eventName);
testFailed.appendInstruction(counterInst);
}
if (inlDec.OSRTestFailed()) {
// note where we're storing the osr barrier instruction
Instruction lastOsrBarrier = parent.getOSRBarrierFromInst(callSite);
Instruction s = BC2IR._osrHelper(lastOsrBarrier, parent);
s.copyPosition(callSite);
testFailed.appendInstruction(s);
testFailed.insertOut(parent.getExit());
} else {
Instruction call = callSite.copyWithoutLinks();
Call.getMethod(call).setIsGuardedInlineOffBranch(true);
call.copyPosition(callSite);
testFailed.appendInstruction(call);
testFailed.insertOut(container.getEpilogue());
// BC2IR.maybeInlineMethod).
if (ebag != null) {
for (Enumeration<BasicBlock> e = ebag.enumerator(); e.hasMoreElements(); ) {
BasicBlock handler = e.nextElement();
testFailed.insertOut(handler);
}
}
testFailed.setCanThrowExceptions();
testFailed.setMayThrowUncaughtException();
}
container.getCfg().linkInCodeOrder(testFailed, container.getEpilogue());
testFailed.setInfrequent();
// Step 5: Patch together all the callees by generating guard blocks
BasicBlock firstIfBlock = testFailed;
// Note: We know that receiver must be a register
// operand (and not a string constant) because we are doing a
// guarded inlining....if it was a string constant we'd have
// been able to inline without a guard.
Operand receiver = Call.getParam(callSite, 0);
MethodOperand mo = Call.getMethod(callSite);
boolean isInterface = mo.isInterface();
if (isInterface) {
if (VM.BuildForIMTInterfaceInvocation) {
RVMType interfaceType = mo.getTarget().getDeclaringClass();
TypeReference recTypeRef = receiver.getType();
RVMClass recType = (RVMClass) recTypeRef.peekType();
// Attempt to avoid inserting the check by seeing if the
// known static type of the receiver implements the interface.
boolean requiresImplementsTest = true;
if (recType != null && recType.isResolved() && !recType.isInterface()) {
byte doesImplement = ClassLoaderProxy.includesType(interfaceType.getTypeRef(), recTypeRef);
requiresImplementsTest = doesImplement != YES;
}
if (requiresImplementsTest) {
RegisterOperand checkedReceiver = parent.getTemps().makeTemp(receiver);
Instruction dtc = TypeCheck.create(MUST_IMPLEMENT_INTERFACE, checkedReceiver, receiver.copy(), new TypeOperand(interfaceType), Call.getGuard(callSite).copy());
dtc.copyPosition(callSite);
checkedReceiver.refine(interfaceType.getTypeRef());
Call.setParam(callSite, 0, checkedReceiver.copyRO());
testFailed.prependInstruction(dtc);
}
}
}
// "logical" test and to share test insertion for interfaces/virtuals.
for (int i = children.length - 1; i >= 0; i--, testFailed = firstIfBlock) {
firstIfBlock = new BasicBlock(callSite.getBytecodeIndex(), callSite.position(), parent.getCfg());
firstIfBlock.setExceptionHandlers(ebag);
BasicBlock lastIfBlock = firstIfBlock;
RVMMethod target = children[i].getMethod();
Instruction tmp;
if (isInterface) {
RVMClass callDeclClass = mo.getTarget().getDeclaringClass();
if (!callDeclClass.isInterface()) {
// the entire compilation.
throw new OptimizingCompilerException("Attempted guarded inline of invoke interface when decl class of target method may not be an interface");
}
// We potentially have to generate IR to perform two tests here:
// (1) Does the receiver object implement callDeclClass?
// (2) Given that it does, is target the method that would
// be invoked for this receiver?
// It is quite common to be able to answer (1) "YES" at compile
// time, in which case we only have to generate IR to establish
// (2) at runtime.
byte doesImplement = ClassLoaderProxy.includesType(callDeclClass.getTypeRef(), target.getDeclaringClass().getTypeRef());
if (doesImplement != YES) {
// implements the interface).
if (parent.getOptions().PRINT_INLINE_REPORT) {
VM.sysWriteln("\t\tRequired additional instanceof " + callDeclClass + " test");
}
firstIfBlock = new BasicBlock(callSite.getBytecodeIndex(), callSite.position(), parent.getCfg());
firstIfBlock.setExceptionHandlers(ebag);
RegisterOperand instanceOfResult = parent.getTemps().makeTempInt();
tmp = InstanceOf.create(INSTANCEOF_NOTNULL, instanceOfResult, new TypeOperand(callDeclClass), receiver.copy(), Call.getGuard(callSite));
tmp.copyPosition(callSite);
firstIfBlock.appendInstruction(tmp);
tmp = IfCmp.create(INT_IFCMP, parent.getTemps().makeTempValidation(), instanceOfResult.copyD2U(), new IntConstantOperand(0), ConditionOperand.EQUAL(), testFailed.makeJumpTarget(), BranchProfileOperand.unlikely());
tmp.copyPosition(callSite);
firstIfBlock.appendInstruction(tmp);
firstIfBlock.insertOut(testFailed);
firstIfBlock.insertOut(lastIfBlock);
container.getCfg().linkInCodeOrder(firstIfBlock, lastIfBlock);
}
}
if (guards[i] == OptOptions.INLINE_GUARD_CLASS_TEST) {
tmp = InlineGuard.create(IG_CLASS_TEST, receiver.copy(), Call.getGuard(callSite).copy(), new TypeOperand(target.getDeclaringClass()), testFailed.makeJumpTarget(), BranchProfileOperand.unlikely());
} else if (guards[i] == OptOptions.INLINE_GUARD_METHOD_TEST) {
// declaring class.
if (isInterface) {
RegisterOperand t = parent.getTemps().makeTempInt();
Instruction test = InstanceOf.create(INSTANCEOF_NOTNULL, t, new TypeOperand(target.getDeclaringClass().getTypeRef()), receiver.copy());
test.copyPosition(callSite);
lastIfBlock.appendInstruction(test);
Instruction cmp = IfCmp.create(INT_IFCMP, parent.getTemps().makeTempValidation(), t.copyD2U(), new IntConstantOperand(0), ConditionOperand.EQUAL(), testFailed.makeJumpTarget(), BranchProfileOperand.unlikely());
cmp.copyPosition(callSite);
lastIfBlock.appendInstruction(cmp);
BasicBlock subclassTest = new BasicBlock(callSite.getBytecodeIndex(), callSite.position(), parent.getCfg());
lastIfBlock.insertOut(testFailed);
lastIfBlock.insertOut(subclassTest);
container.getCfg().linkInCodeOrder(lastIfBlock, subclassTest);
lastIfBlock = subclassTest;
}
tmp = InlineGuard.create(IG_METHOD_TEST, receiver.copy(), Call.getGuard(callSite).copy(), MethodOperand.VIRTUAL(target.getMemberRef().asMethodReference(), target), testFailed.makeJumpTarget(), BranchProfileOperand.unlikely());
} else {
tmp = InlineGuard.create(IG_PATCH_POINT, receiver.copy(), Call.getGuard(callSite).copy(), MethodOperand.VIRTUAL(target.getMemberRef().asMethodReference(), target), testFailed.makeJumpTarget(), inlDec.OSRTestFailed() ? BranchProfileOperand.never() : BranchProfileOperand.unlikely());
}
tmp.copyPosition(callSite);
lastIfBlock.appendInstruction(tmp);
lastIfBlock.insertOut(testFailed);
lastIfBlock.insertOut(children[i].getPrologue());
container.getCfg().linkInCodeOrder(lastIfBlock, children[i].getCfg().firstInCodeOrder());
if (children[i].getEpilogue() != null) {
children[i].getEpilogue().appendInstruction(container.getEpilogue().makeGOTO());
children[i].getEpilogue().insertOut(container.getEpilogue());
}
container.getCfg().linkInCodeOrder(children[i].getCfg().lastInCodeOrder(), testFailed);
}
// Step 6: finish by linking container.prologue & testFailed
container.getPrologue().insertOut(testFailed);
container.getCfg().linkInCodeOrder(container.getPrologue(), testFailed);
return container;
} else {
if (VM.VerifyAssertions)
VM._assert(inlDec.getNumberOfTargets() == 1);
NormalMethod callee = (NormalMethod) inlDec.getTargets()[0];
if (parent.getOptions().PRINT_INLINE_REPORT) {
VM.sysWriteln("\tInline " + callee + " into " + callSite.position().getMethod() + " at bytecode " + callSite.getBytecodeIndex());
}
GenerationContext child = parent.createChildContext(ebag, callee, callSite);
BC2IR.generateHIR(child);
child.transferStateToParent();
return child;
}
}
Also used :
GenerationContext(org.jikesrvm.compilers.opt.bc2ir.GenerationContext)
IntConstantOperand(org.jikesrvm.compilers.opt.ir.operand.IntConstantOperand)
BranchProfileOperand(org.jikesrvm.compilers.opt.ir.operand.BranchProfileOperand)
MethodOperand(org.jikesrvm.compilers.opt.ir.operand.MethodOperand)
TypeOperand(org.jikesrvm.compilers.opt.ir.operand.TypeOperand)
RegisterOperand(org.jikesrvm.compilers.opt.ir.operand.RegisterOperand)
ConditionOperand(org.jikesrvm.compilers.opt.ir.operand.ConditionOperand)
Operand(org.jikesrvm.compilers.opt.ir.operand.Operand)
IntConstantOperand(org.jikesrvm.compilers.opt.ir.operand.IntConstantOperand)
RVMType(org.jikesrvm.classloader.RVMType)
ExceptionHandlerBasicBlock(org.jikesrvm.compilers.opt.ir.ExceptionHandlerBasicBlock)
BasicBlock(org.jikesrvm.compilers.opt.ir.BasicBlock)
Instruction(org.jikesrvm.compilers.opt.ir.Instruction)
MethodOperand(org.jikesrvm.compilers.opt.ir.operand.MethodOperand)
RVMClass(org.jikesrvm.classloader.RVMClass)
RVMMethod(org.jikesrvm.classloader.RVMMethod)
RegisterOperand(org.jikesrvm.compilers.opt.ir.operand.RegisterOperand)
Register(org.jikesrvm.compilers.opt.ir.Register)
NormalMethod(org.jikesrvm.classloader.NormalMethod)
TypeOperand(org.jikesrvm.compilers.opt.ir.operand.TypeOperand)
TypeReference(org.jikesrvm.classloader.TypeReference)
OptimizingCompilerException(org.jikesrvm.compilers.opt.OptimizingCompilerException)
Example 5 with OptimizingCompilerException
use of org.jikesrvm.compilers.opt.OptimizingCompilerException in project JikesRVM by JikesRVM.
the class EscapeTransformations method getAggregateReplacer.
/**
* Generate an object which will perform scalar replacement of
* an aggregate allocated by a given instruction
*
* <p> PRECONDITION: objects returned by this allocation site do NOT escape
* the current method
*
* @param inst the allocation site
* @param ir controlling ir
* @return an AggregateReplacer specialized to the allocation site,
* null if no legal transformation found
*/
private AggregateReplacer getAggregateReplacer(Instruction inst, IR ir) {
OptOptions options = ir.options;
RVMType t = null;
if (inst.getOpcode() == NEW_opcode) {
t = New.getType(inst).getVMType();
} else if (inst.getOpcode() == NEWARRAY_opcode) {
t = NewArray.getType(inst).getVMType();
} else {
throw new OptimizingCompilerException("Logic Error in EscapeTransformations");
}
// first attempt to perform scalar replacement for an object
if (t.isClassType() && options.ESCAPE_SCALAR_REPLACE_AGGREGATES) {
return ObjectReplacer.getReplacer(inst, ir);
}
// attempt to perform scalar replacement on a short array
if (t.isArrayType() && options.ESCAPE_SCALAR_REPLACE_AGGREGATES) {
return ShortArrayReplacer.getReplacer(inst, ir);
}
return null;
}
Also used :
RVMType(org.jikesrvm.classloader.RVMType)
OptOptions(org.jikesrvm.compilers.opt.OptOptions)
OptimizingCompilerException(org.jikesrvm.compilers.opt.OptimizingCompilerException)
Aggregations
OptimizingCompilerException (org.jikesrvm.compilers.opt.OptimizingCompilerException)47
RegisterOperand (org.jikesrvm.compilers.opt.ir.operand.RegisterOperand)25
Operand (org.jikesrvm.compilers.opt.ir.operand.Operand)18
Instruction (org.jikesrvm.compilers.opt.ir.Instruction)17
Register (org.jikesrvm.compilers.opt.ir.Register)16
IntConstantOperand (org.jikesrvm.compilers.opt.ir.operand.IntConstantOperand)14
ConditionOperand (org.jikesrvm.compilers.opt.ir.operand.ConditionOperand)11
LongConstantOperand (org.jikesrvm.compilers.opt.ir.operand.LongConstantOperand)11
MethodOperand (org.jikesrvm.compilers.opt.ir.operand.MethodOperand)11
TrapCodeOperand (org.jikesrvm.compilers.opt.ir.operand.TrapCodeOperand)10
TrueGuardOperand (org.jikesrvm.compilers.opt.ir.operand.TrueGuardOperand)10
BranchProfileOperand (org.jikesrvm.compilers.opt.ir.operand.BranchProfileOperand)9
ConstantOperand (org.jikesrvm.compilers.opt.ir.operand.ConstantOperand)9
LocationOperand (org.jikesrvm.compilers.opt.ir.operand.LocationOperand)9
TypeReference (org.jikesrvm.classloader.TypeReference)8
AddressConstantOperand (org.jikesrvm.compilers.opt.ir.operand.AddressConstantOperand)8
BranchOperand (org.jikesrvm.compilers.opt.ir.operand.BranchOperand)8
DoubleConstantOperand (org.jikesrvm.compilers.opt.ir.operand.DoubleConstantOperand)6
FloatConstantOperand (org.jikesrvm.compilers.opt.ir.operand.FloatConstantOperand)6
Offset (org.vmmagic.unboxed.Offset)6
