Examples with MemoryOperand org.jikesrvm.compilers.opt.ir.operand.MemoryOperand used on opensource projects

Example 1 with MemoryOperand

use of org.jikesrvm.compilers.opt.ir.operand.MemoryOperand in project JikesRVM by JikesRVM.

the class AssemblerBase method operandCost.

private int operandCost(Operand op, boolean shortFormImmediate) {
    if (op instanceof MemoryOperand) {
        MemoryOperand mop = (MemoryOperand) op;
        // If it's a 2byte mem location, we're going to need an override prefix
        int prefix = mop.size == 2 ? 1 : 0;
        // Deal with EBP wierdness
        if (mop.base != null && mop.base.getRegister() == EBP) {
            if (mop.index != null) {
                // forced into SIB + 32 bit displacement no matter what disp is
                return prefix + 5;
            }
            if (fits(mop.disp, 8)) {
                return prefix + 1;
            } else {
                return prefix + 4;
            }
        }
        if (mop.index != null && mop.index.getRegister() == EBP) {
            // forced into SIB + 32 bit displacement no matter what disp is
            return prefix + 5;
        }
        // Deal with ESP wierdness -- requires SIB byte even when index is null
        if (mop.base != null && mop.base.getRegister() == ESP) {
            if (fits(mop.disp, 8)) {
                return prefix + 2;
            } else {
                return prefix + 5;
            }
        }
        if (mop.index == null) {
            // just displacement to worry about
            if (mop.disp.isZero()) {
                return prefix + 0;
            } else if (fits(mop.disp, 8)) {
                return prefix + 1;
            } else {
                return prefix + 4;
            }
        } else {
            // have a SIB
            if (mop.base == null && mop.scale != 0) {
                // forced to 32 bit displacement even if it would fit in 8
                return prefix + 5;
            } else {
                if (mop.disp.isZero()) {
                    return prefix + 1;
                } else if (fits(mop.disp, 8)) {
                    return prefix + 2;
                } else {
                    return prefix + 5;
                }
            }
        }
    } else if (op instanceof IntConstantOperand) {
        if (shortFormImmediate && fits(((IntConstantOperand) op).value, 8)) {
            return 1;
        } else {
            return 4;
        }
    } else {
        return 0;
    }
}

Example 2 with MemoryOperand

use of org.jikesrvm.compilers.opt.ir.operand.MemoryOperand in project JikesRVM by JikesRVM.

the class AssemblerBase method isQuad.

/**
 * Does the given instruction operate upon quad-sized data
 * <em>for the purposes of assembling the instruction</em>?
 * The opt compiler does not represent the size of register data, so
 * it is necessary to determine whether to emit a quad instruction.
 * As described above, this method is only concerned with quad data
 * that changes the instruction. For example, this method will return
 * {@code false} for {@code FSTP}. {@code FSTP} operates on quad-data
 * but the instruction's operation is the same for 32-bit and 64-bit
 * mode, so it is not a quad instruction for the purposes of this method.
 * <p>
 * This method typically looks at the memory operand, if any, and
 * checks whether that is a byte. This method also recognizes
 * the operator convention that __q on the end of the operator
 * name means operate upon quad data. Moreover, it looks at data types
 * for x64.
 *
 * @param inst the instruction being queried
 * @return {@code true} if instruction operates upon quad data <b>AND</b>
 *  is treated as a quad instruction for the purpose of assembling the
 *  machine code
 */
boolean isQuad(Instruction inst) {
    for (Operator opr : quadSizeOperators) {
        if (opr == inst.operator()) {
            return true;
        }
    }
    if (VM.BuildFor32Addr) {
        for (int i = 0; i < inst.getNumberOfOperands(); i++) {
            Operand op = inst.getOperand(i);
            if (op instanceof MemoryOperand) {
                return ((MemoryOperand) op).size == 8;
            }
        }
    } else {
        // 64-bit
        for (int i = 0; i < inst.getNumberOfOperands(); i++) {
            Operand op = inst.getOperand(i);
            if (op == null) {
                // The operand may only be null for a few cases.
                if (VM.VerifyAssertions) {
                    // Return has 2 return operands on IA32 because it
                    // must be able to return a 64-bit value. On x64, only
                    // one of the operands is needed, the other one is null.
                    boolean isReturn = MIR_Return.conforms(inst);
                    if (isReturn) {
                        VM._assert(i == MIR_Return.indexOfVal2(inst));
                    }
                    // Guards may be null for divides
                    boolean isDivide = MIR_Divide.conforms(inst);
                    if (isDivide) {
                        VM._assert(i == MIR_Divide.indexOfGuard(inst));
                    }
                    // For all other cases, all operands must be non null
                    String msg = inst.toString();
                    VM._assert(isReturn || isDivide, msg);
                }
                continue;
            }
            if (op.isLong() || op.isRef() || op.isAddress()) {
                return true;
            }
            boolean quadMemOp = false;
            if (op instanceof MemoryOperand) {
                quadMemOp = op.asMemory().size == 8;
            } else if (op instanceof StackLocationOperand) {
                quadMemOp = op.asStackLocation().getSize() == 8;
            }
            // even if this one won't
            if (quadMemOp) {
                return true;
            }
        }
    }
    return false;
}

Example 3 with MemoryOperand

use of org.jikesrvm.compilers.opt.ir.operand.MemoryOperand in project JikesRVM by JikesRVM.

the class FinalMIRExpansion method expandYieldpoint.

private static void expandYieldpoint(Instruction s, IR ir, RVMMethod meth, IA32ConditionOperand ypCond) {
    // split the basic block after the yieldpoint, create a new
    // block at the end of the IR to hold the yieldpoint,
    // remove the yieldpoint (to prepare to out it in the new block at the end)
    BasicBlock thisBlock = s.getBasicBlock();
    BasicBlock nextBlock = thisBlock.splitNodeWithLinksAt(s, ir);
    BasicBlock yieldpoint = thisBlock.createSubBlock(s.getBytecodeIndex(), ir, 0);
    thisBlock.insertOut(yieldpoint);
    yieldpoint.insertOut(nextBlock);
    ir.cfg.addLastInCodeOrder(yieldpoint);
    s.remove();
    // change thread switch instruction into call to thread switch routine
    // NOTE: must make s the call instruction: it is the GC point!
    // must also inform the GCMap that s has been moved!!!
    Offset offset = meth.getOffset();
    LocationOperand loc = new LocationOperand(offset);
    Operand guard = TG();
    Operand target;
    if (JTOC_REGISTER == null) {
        target = MemoryOperand.D(Magic.getTocPointer().plus(offset), (byte) BYTES_IN_ADDRESS, loc, guard);
    } else {
        target = MemoryOperand.BD(ir.regpool.makeTocOp().asRegister(), offset, (byte) BYTES_IN_ADDRESS, loc, guard);
    }
    MIR_Call.mutate0(s, CALL_SAVE_VOLATILE, null, null, target, MethodOperand.STATIC(meth));
    yieldpoint.appendInstruction(s);
    ir.MIRInfo.gcIRMap.moveToEnd(s);
    yieldpoint.appendInstruction(MIR_Branch.create(IA32_JMP, nextBlock.makeJumpTarget()));
    // Check to see if threadSwitch requested
    Offset tsr = Entrypoints.takeYieldpointField.getOffset();
    MemoryOperand M = MemoryOperand.BD(ir.regpool.makeTROp(), tsr, (byte) 4, null, null);
    thisBlock.appendInstruction(MIR_Compare.create(IA32_CMP, M, IC(0)));
    thisBlock.appendInstruction(MIR_CondBranch.create(IA32_JCC, ypCond, yieldpoint.makeJumpTarget(), BranchProfileOperand.never()));
}

Example 4 with MemoryOperand

use of org.jikesrvm.compilers.opt.ir.operand.MemoryOperand in project JikesRVM by JikesRVM.

the class FinalMIRExpansion method expand.

/**
 * @param ir the IR to expand
 * @return return value is garbage for IA32
 */
public static int expand(IR ir) {
    PhysicalRegisterSet phys = ir.regpool.getPhysicalRegisterSet().asIA32();
    MachineCodeOffsets mcOffsets = ir.MIRInfo.mcOffsets;
    for (Instruction next, p = ir.firstInstructionInCodeOrder(); p != null; p = next) {
        next = p.nextInstructionInCodeOrder();
        mcOffsets.setMachineCodeOffset(p, -1);
        switch(p.getOpcode()) {
            case IA32_MOVAPS_opcode:
                // a reg-reg move turned into a memory move where we can't guarantee alignment
                if (MIR_Move.getResult(p).isMemory() || MIR_Move.getValue(p).isMemory()) {
                    MIR_Move.mutate(p, IA32_MOVSS, MIR_Move.getClearResult(p), MIR_Move.getClearValue(p));
                }
                break;
            case IA32_MOVAPD_opcode:
                // a reg-reg move turned into a memory move where we can't guarantee alignment
                if (MIR_Move.getResult(p).isMemory() || MIR_Move.getValue(p).isMemory()) {
                    MIR_Move.mutate(p, IA32_MOVSD, MIR_Move.getClearResult(p), MIR_Move.getClearValue(p));
                }
                break;
            case IA32_TEST_opcode:
                // must be first; we can just commute it here.
                if (MIR_Test.getVal2(p).isMemory()) {
                    Operand tmp = MIR_Test.getClearVal1(p);
                    MIR_Test.setVal1(p, MIR_Test.getClearVal2(p));
                    MIR_Test.setVal2(p, tmp);
                }
                break;
            case NULL_CHECK_opcode:
                {
                    // mutate this into a TRAPIF, and then fall through to the the
                    // TRAP_IF case.
                    Operand ref = NullCheck.getRef(p);
                    MIR_TrapIf.mutate(p, IA32_TRAPIF, null, ref.copy(), IC(0), IA32ConditionOperand.EQ(), TrapCodeOperand.NullPtr());
                }
            // There is no break statement here on purpose!
            case IA32_TRAPIF_opcode:
                {
                    // split the basic block right before the IA32_TRAPIF
                    BasicBlock thisBlock = p.getBasicBlock();
                    BasicBlock trap = thisBlock.createSubBlock(p.getBytecodeIndex(), ir, 0f);
                    thisBlock.insertOut(trap);
                    BasicBlock nextBlock = thisBlock.splitNodeWithLinksAt(p, ir);
                    thisBlock.insertOut(trap);
                    TrapCodeOperand tc = MIR_TrapIf.getClearTrapCode(p);
                    p.remove();
                    mcOffsets.setMachineCodeOffset(nextBlock.firstInstruction(), -1);
                    // add code to thisBlock to conditionally jump to trap
                    Instruction cmp = MIR_Compare.create(IA32_CMP, MIR_TrapIf.getVal1(p).copy(), MIR_TrapIf.getVal2(p).copy());
                    if (p.isMarkedAsPEI()) {
                        // The trap if was explictly marked, which means that it has
                        // a memory operand into which we've folded a null check.
                        // Actually need a GC map for both the compare and the INT.
                        cmp.markAsPEI();
                        cmp.copyPosition(p);
                        ir.MIRInfo.gcIRMap.insertTwin(p, cmp);
                    }
                    thisBlock.appendInstruction(cmp);
                    thisBlock.appendInstruction(MIR_CondBranch.create(IA32_JCC, (IA32ConditionOperand) MIR_TrapIf.getCond(p).copy(), trap.makeJumpTarget(), null));
                    // add block at end to hold trap instruction, and
                    // insert trap sequence
                    ir.cfg.addLastInCodeOrder(trap);
                    if (tc.isArrayBounds()) {
                        // attempt to store index expression in processor object for
                        // C trap handler
                        Operand index = MIR_TrapIf.getVal2(p);
                        if (!(index instanceof RegisterOperand || index instanceof IntConstantOperand)) {
                            // index was spilled, and
                            index = IC(0xdeadbeef);
                        // we can't get it back here.
                        }
                        MemoryOperand mo = MemoryOperand.BD(ir.regpool.makeTROp(), ArchEntrypoints.arrayIndexTrapParamField.getOffset(), (byte) 4, null, null);
                        trap.appendInstruction(MIR_Move.create(IA32_MOV, mo, index.copy()));
                    }
                    // NOTE: must make p the trap instruction: it is the GC point!
                    // IMPORTANT: must also inform the GCMap that the instruction has
                    // been moved!!!
                    trap.appendInstruction(MIR_Trap.mutate(p, IA32_INT, null, tc));
                    ir.MIRInfo.gcIRMap.moveToEnd(p);
                    if (tc.isStackOverflow()) {
                        // only stackoverflow traps resume at next instruction.
                        trap.appendInstruction(MIR_Branch.create(IA32_JMP, nextBlock.makeJumpTarget()));
                    }
                }
                break;
            case IA32_FMOV_ENDING_LIVE_RANGE_opcode:
                {
                    Operand result = MIR_Move.getResult(p);
                    Operand value = MIR_Move.getValue(p);
                    if (result.isRegister() && value.isRegister()) {
                        if (result.similar(value)) {
                            // eliminate useless move
                            p.remove();
                        } else {
                            int i = PhysicalRegisterSet.getFPRIndex(result.asRegister().getRegister());
                            int j = PhysicalRegisterSet.getFPRIndex(value.asRegister().getRegister());
                            if (i == 0) {
                                MIR_XChng.mutate(p, IA32_FXCH, result, value);
                            } else if (j == 0) {
                                MIR_XChng.mutate(p, IA32_FXCH, value, result);
                            } else {
                                expandFmov(p, phys);
                            }
                        }
                    } else {
                        expandFmov(p, phys);
                    }
                    break;
                }
            case DUMMY_DEF_opcode:
            case DUMMY_USE_opcode:
            case REQUIRE_ESP_opcode:
            case ADVISE_ESP_opcode:
                p.remove();
                break;
            case IA32_FMOV_opcode:
                expandFmov(p, phys);
                break;
            case IA32_MOV_opcode:
                // Convert 0L to 0 to allow optimization into XOR.
                if (MIR_Move.getResult(p).isRegister() && MIR_Move.getValue(p).isLongConstant() && MIR_Move.getValue(p).asLongConstant().value == 0L) {
                    MIR_Move.setValue(p, IC(0));
                }
                // Replace result = IA32_MOV 0 with result = IA32_XOR result, result
                if (MIR_Move.getResult(p).isRegister() && MIR_Move.getValue(p).isIntConstant() && MIR_Move.getValue(p).asIntConstant().value == 0) {
                    // Calculate what flags are defined in coming instructions before a use of a flag or BBend
                    Instruction x = next;
                    int futureDefs = 0;
                    while (!BBend.conforms(x) && !PhysicalDefUse.usesEFLAGS(x.operator())) {
                        futureDefs |= x.operator().implicitDefs;
                        x = x.nextInstructionInCodeOrder();
                    }
                    // If the flags will be destroyed prior to use or we reached the end of the basic block
                    if (BBend.conforms(x) || (futureDefs & PhysicalDefUse.maskAF_CF_OF_PF_SF_ZF) == PhysicalDefUse.maskAF_CF_OF_PF_SF_ZF) {
                        Operand result = MIR_Move.getClearResult(p);
                        MIR_BinaryAcc.mutate(p, IA32_XOR, result, result.copy());
                    }
                }
                break;
            case IA32_SET__B_opcode:
                // Replace <cmp>, set__b, movzx__b with xor, <cmp>, set__b
                if (MIR_Set.getResult(p).isRegister() && MIR_Unary.conforms(next) && (next.operator() == IA32_MOVZX__B) && MIR_Unary.getResult(next).isRegister() && MIR_Unary.getVal(next).similar(MIR_Unary.getResult(next)) && MIR_Unary.getVal(next).similar(MIR_Set.getResult(p))) {
                    // Find instruction in this basic block that defines flags
                    Instruction x = p.prevInstructionInCodeOrder();
                    Operand result = MIR_Unary.getResult(next);
                    boolean foundCmp = false;
                    outer: while (!Label.conforms(x)) {
                        Enumeration<Operand> e = x.getUses();
                        while (e.hasMoreElements()) {
                            // used by the <cmp> or intervening instruction
                            if (e.nextElement().similar(result)) {
                                break outer;
                            }
                        }
                        if (PhysicalDefUse.definesEFLAGS(x.operator()) && !PhysicalDefUse.usesEFLAGS(x.operator())) {
                            // we found a <cmp> that doesn't use the result or the flags
                            // that would be clobbered by the xor
                            foundCmp = true;
                            break outer;
                        }
                        x = x.prevInstructionInCodeOrder();
                    }
                    if (foundCmp) {
                        // We found the <cmp>, mutate the movzx__b into an xor and insert it before the <cmp>
                        next.remove();
                        MIR_BinaryAcc.mutate(next, IA32_XOR, result, MIR_Unary.getVal(next));
                        x.insertBefore(next);
                        // get ready for the next instruction
                        next = p.nextInstructionInCodeOrder();
                    }
                }
                break;
            case IA32_LEA_opcode:
                {
                    // Sometimes we're over eager in BURS in using LEAs and after register
                    // allocation we can simplify to the accumulate form
                    // replace reg1 = LEA [reg1 + reg2] with reg1 = reg1 + reg2
                    // replace reg1 = LEA [reg1 + c1] with reg1 = reg1 + c1
                    // replace reg1 = LEA [reg1 << c1] with reg1 = reg1 << c1
                    MemoryOperand value = MIR_Lea.getValue(p);
                    RegisterOperand result = MIR_Lea.getResult(p);
                    if ((value.base != null && value.base.getRegister() == result.getRegister()) || (value.index != null && value.index.getRegister() == result.getRegister())) {
                        // Calculate what flags are defined in coming instructions before a use of a flag or BBend
                        Instruction x = next;
                        int futureDefs = 0;
                        while (!BBend.conforms(x) && !PhysicalDefUse.usesEFLAGS(x.operator())) {
                            futureDefs |= x.operator().implicitDefs;
                            x = x.nextInstructionInCodeOrder();
                        }
                        // If the flags will be destroyed prior to use or we reached the end of the basic block
                        if (BBend.conforms(x) || (futureDefs & PhysicalDefUse.maskAF_CF_OF_PF_SF_ZF) == PhysicalDefUse.maskAF_CF_OF_PF_SF_ZF) {
                            if (value.base != null && value.index != null && value.index.getRegister() == result.getRegister() && value.disp.isZero() && value.scale == 0) {
                                // reg1 = lea [base + reg1] -> add reg1, base
                                MIR_BinaryAcc.mutate(p, IA32_ADD, result, value.base);
                            } else if (value.base != null && value.base.getRegister() == result.getRegister() && value.index != null && value.disp.isZero() && value.scale == 0) {
                                // reg1 = lea [reg1 + index] -> add reg1, index
                                MIR_BinaryAcc.mutate(p, IA32_ADD, result, value.index);
                            } else if (value.base != null && value.base.getRegister() == result.getRegister() && value.index == null) {
                                if (VM.VerifyAssertions)
                                    VM._assert(fits(value.disp, 32));
                                // reg1 = lea [reg1 + disp] -> add reg1, disp
                                MIR_BinaryAcc.mutate(p, IA32_ADD, result, IC(value.disp.toInt()));
                            } else if (value.base == null && value.index != null && value.index.getRegister() == result.getRegister() && value.scale == 0) {
                                if (VM.VerifyAssertions)
                                    VM._assert(fits(value.disp, 32));
                                // reg1 = lea [reg1 + disp] -> add reg1, disp
                                MIR_BinaryAcc.mutate(p, IA32_ADD, result, IC(value.disp.toInt()));
                            } else if (value.base == null && value.index != null && value.index.getRegister() == result.getRegister() && value.disp.isZero()) {
                                // reg1 = lea [reg1 << scale] -> shl reg1, scale
                                if (value.scale == 0) {
                                    p.remove();
                                } else if (value.scale == 1) {
                                    MIR_BinaryAcc.mutate(p, IA32_ADD, result, value.index);
                                } else {
                                    MIR_BinaryAcc.mutate(p, IA32_SHL, result, IC(value.scale));
                                }
                            }
                        }
                    }
                }
                break;
            case IA32_FCLEAR_opcode:
                expandFClear(p, ir);
                break;
            case IA32_JCC2_opcode:
                p.insertBefore(MIR_CondBranch.create(IA32_JCC, MIR_CondBranch2.getClearCond1(p), MIR_CondBranch2.getClearTarget1(p), MIR_CondBranch2.getClearBranchProfile1(p)));
                MIR_CondBranch.mutate(p, IA32_JCC, MIR_CondBranch2.getClearCond2(p), MIR_CondBranch2.getClearTarget2(p), MIR_CondBranch2.getClearBranchProfile2(p));
                break;
            case CALL_SAVE_VOLATILE_opcode:
                p.changeOperatorTo(IA32_CALL);
                break;
            case IA32_LOCK_CMPXCHG_opcode:
                p.insertBefore(MIR_Empty.create(IA32_LOCK));
                p.changeOperatorTo(IA32_CMPXCHG);
                break;
            case IA32_LOCK_CMPXCHG8B_opcode:
                p.insertBefore(MIR_Empty.create(IA32_LOCK));
                p.changeOperatorTo(IA32_CMPXCHG8B);
                break;
            case YIELDPOINT_PROLOGUE_opcode:
                expandYieldpoint(p, ir, Entrypoints.optThreadSwitchFromPrologueMethod, IA32ConditionOperand.NE());
                break;
            case YIELDPOINT_EPILOGUE_opcode:
                expandYieldpoint(p, ir, Entrypoints.optThreadSwitchFromEpilogueMethod, IA32ConditionOperand.NE());
                break;
            case YIELDPOINT_BACKEDGE_opcode:
                expandYieldpoint(p, ir, Entrypoints.optThreadSwitchFromBackedgeMethod, IA32ConditionOperand.GT());
                break;
            case YIELDPOINT_OSR_opcode:
                // must yield, does not check threadSwitch request
                expandUnconditionalYieldpoint(p, ir, Entrypoints.optThreadSwitchFromOsrOptMethod);
                break;
        }
    }
    return 0;
}

Example 5 with MemoryOperand

use of org.jikesrvm.compilers.opt.ir.operand.MemoryOperand in project JikesRVM by JikesRVM.

the class RewriteMemoryOperandsWithOversizedDisplacements method perform.

@Override
public void perform(IR ir) {
    for (Instruction inst = ir.firstInstructionInCodeOrder(); inst != null; inst = inst.nextInstructionInCodeOrder()) {
        for (int i = 0; i < inst.getNumberOfOperands(); i++) {
            Operand op = inst.getOperand(i);
            if (op instanceof MemoryOperand) {
                MemoryOperand mo = (MemoryOperand) op;
                disp64MemOperandConversion(ir, inst, mo);
            }
        }
    }
}