use of org.jikesrvm.compilers.opt.ir.operand.Operand in project JikesRVM by JikesRVM.
the class BURS_Helpers method SSE2_COP.
/**
* BURS expansion of a commutative SSE2 operation.
*
* @param operator the operator
* @param s the instruction in question
* @param result the instruction's result operand
* @param val1 the instruction's first value operand
* @param val2 the instruction's second value operand
*/
protected void SSE2_COP(Operator operator, Instruction s, Operand result, Operand val1, Operand val2) {
if (VM.VerifyAssertions)
opt_assert(result.isRegister());
// constants into val2
if (val2.similar(result)) {
Operand temp = val1;
val1 = val2;
val2 = temp;
}
// Do we need to move prior to the operator - result = val1
if (!result.similar(val1)) {
EMIT(CPOS(s, MIR_Move.create(SSE2_MOVE(result), result.copy(), val1)));
}
EMIT(MIR_BinaryAcc.mutate(s, operator, result, val2));
}
use of org.jikesrvm.compilers.opt.ir.operand.Operand in project JikesRVM by JikesRVM.
the class BURS_Helpers method RESOLVE.
/**
* Expansion of RESOLVE. Dynamic link point. Build up MIR instructions for
* Resolve.
*
* @param s the instruction to expand
*/
protected final void RESOLVE(Instruction s) {
Operand target = loadFromJTOC(burs.ir, Entrypoints.optResolveMethod.getOffset(), VM.BuildFor32Addr ? DW : QW);
EMIT(CPOS(s, MIR_Call.mutate0(s, CALL_SAVE_VOLATILE, null, null, target, MethodOperand.STATIC(Entrypoints.optResolveMethod))));
}
use of org.jikesrvm.compilers.opt.ir.operand.Operand in project JikesRVM by JikesRVM.
the class ComplexLIR2MIRExpansion method process64BitImmediateValues.
public static void process64BitImmediateValues(IR ir) {
for (Instruction s = ir.firstInstructionInCodeOrder(); s != null; s = s.nextInstructionInCodeOrder()) {
char opcode = s.getOpcode();
if (opcode == IMMQ_MOV_opcode)
continue;
if (MIR_Move.conforms(s)) {
Operand moveResult = MIR_Move.getResult(s);
if (opcode == IA32_MOV_opcode && moveResult.isRegister()) {
Operand value = MIR_Move.getValue(s);
if (value.isLongConstant()) {
LongConstantOperand lc = (LongConstantOperand) value;
if (!Bits.fits(lc.value, 32)) {
MIR_Move.mutate(s, IMMQ_MOV, moveResult, value);
continue;
}
}
}
}
for (Enumeration<Operand> ops = s.getOperands(); ops.hasMoreElements(); ) {
Operand op = ops.nextElement();
if (op.isLongConstant()) {
LongConstantOperand lc = (LongConstantOperand) op;
if (!Bits.fits(lc.value, 32)) {
RegisterOperand temp = ir.regpool.makeTempLong();
if (lc.convertedFromRef()) {
temp.flagAsConvertedFromRef();
}
s.insertBefore(MIR_Move.create(IMMQ_MOV, temp, lc.copy()));
s.replaceOperand(lc, temp.copyD2U());
}
}
}
}
}
use of org.jikesrvm.compilers.opt.ir.operand.Operand in project JikesRVM by JikesRVM.
the class ComplexLIR2MIRExpansion method long_ushr.
private static Instruction long_ushr(Instruction s, IR ir) {
Instruction nextInstr = s.nextInstructionInCodeOrder();
while (Label.conforms(nextInstr) || BBend.conforms(nextInstr)) {
nextInstr = nextInstr.nextInstructionInCodeOrder();
}
// we need 4 basic blocks
// 1: the current block that does a test if the shift is > 32
// 2: a block to perform a shift in the range 32 to 63
// 3: a block to perform a shift in the range 0 to 31
// 4: the next basic block
BasicBlock testBB = s.getBasicBlock();
BasicBlock nextBB = testBB.splitNodeAt(s, ir);
ir.cfg.linkInCodeOrder(testBB, nextBB);
BasicBlock shift32BB = testBB.splitNodeAt(s, ir);
ir.cfg.linkInCodeOrder(testBB, shift32BB);
BasicBlock shift64BB = testBB.splitNodeAt(s, ir);
ir.cfg.linkInCodeOrder(testBB, shift64BB);
// Source registers
Register lhsReg = Binary.getClearResult(s).getRegister();
Register lowlhsReg = ir.regpool.getSecondReg(lhsReg);
Operand val1 = Binary.getClearVal1(s);
Register rhsReg;
Register lowrhsReg;
if (val1.isRegister()) {
rhsReg = val1.asRegister().getRegister();
lowrhsReg = ir.regpool.getSecondReg(rhsReg);
} else {
// shift is of a constant so set up registers
int low = val1.asLongConstant().lower32();
int high = val1.asLongConstant().upper32();
testBB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lowlhsReg, TypeReference.Int), IC(low))));
testBB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lhsReg, TypeReference.Int), IC(high))));
rhsReg = lhsReg;
lowrhsReg = lowlhsReg;
}
// ecx = shift amount
Register ecx = phys(ir).getECX();
testBB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(ecx, TypeReference.Int), Binary.getClearVal2(s))));
// Determine shift of 32 to 63 or 0 to 31
testBB.appendInstruction(CPOS(s, MIR_Test.create(IA32_TEST, new RegisterOperand(ecx, TypeReference.Int), IC(32))));
// if (ecx & 32 == 0) goto shift32BB
testBB.appendInstruction(CPOS(s, MIR_CondBranch.create(IA32_JCC, IA32ConditionOperand.EQ(), shift32BB.makeJumpTarget(), BranchProfileOperand.likely())));
testBB.insertOut(shift32BB);
// fall-through
testBB.insertOut(shift64BB);
// Perform shift in the range 32 to 63
shift64BB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lowlhsReg, TypeReference.Int), new RegisterOperand(rhsReg, TypeReference.Int))));
shift64BB.appendInstruction(CPOS(s, MIR_BinaryAcc.create(IA32_SHR, new RegisterOperand(lowlhsReg, TypeReference.Int), new RegisterOperand(ecx, TypeReference.Int))));
shift64BB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lhsReg, TypeReference.Int), IC(0))));
shift64BB.appendInstruction(CPOS(s, MIR_Branch.create(IA32_JMP, nextBB.makeJumpTarget())));
shift64BB.insertOut(nextBB);
// Perform shift in the range 0 to 31
if (lhsReg != rhsReg) {
shift32BB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lhsReg, TypeReference.Int), new RegisterOperand(rhsReg, TypeReference.Int))));
shift32BB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lowlhsReg, TypeReference.Int), new RegisterOperand(lowrhsReg, TypeReference.Int))));
}
shift32BB.appendInstruction(CPOS(s, MIR_DoubleShift.create(IA32_SHRD, new RegisterOperand(lowlhsReg, TypeReference.Int), new RegisterOperand(lhsReg, TypeReference.Int), new RegisterOperand(ecx, TypeReference.Int))));
shift32BB.appendInstruction(CPOS(s, MIR_BinaryAcc.create(IA32_SHR, new RegisterOperand(lhsReg, TypeReference.Int), new RegisterOperand(ecx, TypeReference.Int))));
shift32BB.insertOut(nextBB);
s.remove();
return nextInstr;
}
use of org.jikesrvm.compilers.opt.ir.operand.Operand in project JikesRVM by JikesRVM.
the class ComplexLIR2MIRExpansion method long_shl.
private static Instruction long_shl(Instruction s, IR ir) {
Instruction nextInstr = s.nextInstructionInCodeOrder();
while (Label.conforms(nextInstr) || BBend.conforms(nextInstr)) {
nextInstr = nextInstr.nextInstructionInCodeOrder();
}
// we need 4 basic blocks
// 1: the current block that does a test if the shift is > 32
// 2: a block to perform a shift in the range 32 to 63
// 3: a block to perform a shift in the range 0 to 31
// 4: the next basic block
BasicBlock testBB = s.getBasicBlock();
BasicBlock nextBB = testBB.splitNodeAt(s, ir);
ir.cfg.linkInCodeOrder(testBB, nextBB);
BasicBlock shift32BB = testBB.splitNodeAt(s, ir);
ir.cfg.linkInCodeOrder(testBB, shift32BB);
BasicBlock shift64BB = testBB.splitNodeAt(s, ir);
ir.cfg.linkInCodeOrder(testBB, shift64BB);
// Source registers
Register lhsReg = Binary.getClearResult(s).getRegister();
Register lowlhsReg = ir.regpool.getSecondReg(lhsReg);
Operand val1 = Binary.getClearVal1(s);
Register rhsReg;
Register lowrhsReg;
if (val1.isRegister()) {
rhsReg = val1.asRegister().getRegister();
lowrhsReg = ir.regpool.getSecondReg(rhsReg);
} else {
// shift is of a constant so set up registers
int low = val1.asLongConstant().lower32();
int high = val1.asLongConstant().upper32();
testBB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lowlhsReg, TypeReference.Int), IC(low))));
testBB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lhsReg, TypeReference.Int), IC(high))));
rhsReg = lhsReg;
lowrhsReg = lowlhsReg;
}
// ecx = shift amount
Register ecx = phys(ir).getECX();
testBB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(ecx, TypeReference.Int), Binary.getClearVal2(s))));
// Determine shift of 32 to 63 or 0 to 31
testBB.appendInstruction(CPOS(s, MIR_Test.create(IA32_TEST, new RegisterOperand(ecx, TypeReference.Int), IC(32))));
// if (ecx & 32 == 0) goto shift32BB
testBB.appendInstruction(CPOS(s, MIR_CondBranch.create(IA32_JCC, IA32ConditionOperand.EQ(), shift32BB.makeJumpTarget(), BranchProfileOperand.likely())));
testBB.insertOut(shift32BB);
// fall-through
testBB.insertOut(shift64BB);
// Perform shift in the range 32 to 63
shift64BB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lhsReg, TypeReference.Int), new RegisterOperand(lowrhsReg, TypeReference.Int))));
shift64BB.appendInstruction(CPOS(s, MIR_BinaryAcc.create(IA32_SHL, new RegisterOperand(lhsReg, TypeReference.Int), new RegisterOperand(ecx, TypeReference.Int))));
shift64BB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lowlhsReg, TypeReference.Int), IC(0))));
shift64BB.appendInstruction(CPOS(s, MIR_Branch.create(IA32_JMP, nextBB.makeJumpTarget())));
shift64BB.insertOut(nextBB);
// Perform shift in the range 0 to 31
if (lhsReg != rhsReg) {
shift32BB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lhsReg, TypeReference.Int), new RegisterOperand(rhsReg, TypeReference.Int))));
shift32BB.appendInstruction(CPOS(s, MIR_Move.create(IA32_MOV, new RegisterOperand(lowlhsReg, TypeReference.Int), new RegisterOperand(lowrhsReg, TypeReference.Int))));
}
shift32BB.appendInstruction(CPOS(s, MIR_DoubleShift.create(IA32_SHLD, new RegisterOperand(lhsReg, TypeReference.Int), new RegisterOperand(lowlhsReg, TypeReference.Int), new RegisterOperand(ecx, TypeReference.Int))));
shift32BB.appendInstruction(CPOS(s, MIR_BinaryAcc.create(IA32_SHL, new RegisterOperand(lowlhsReg, TypeReference.Int), new RegisterOperand(ecx, TypeReference.Int))));
shift32BB.insertOut(nextBB);
s.remove();
return nextInstr;
}
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