Examples with PowerPCConditionOperand org.jikesrvm.compilers.opt.ir.operand.ppc.PowerPCConditionOperand used on opensource projects

Example 1 with PowerPCConditionOperand

use of org.jikesrvm.compilers.opt.ir.operand.ppc.PowerPCConditionOperand in project JikesRVM by JikesRVM.

the class BURS_Helpers method CMP2.

/**
 * emit basic code to handle an INT_IFCMP2 when no folding
 * of the compare into some other computation is possible.
 */
protected final void CMP2(Instruction s, RegisterOperand val1, Operand val2, ConditionOperand cond1, ConditionOperand cond2, boolean immediate) {
    Operator op1;
    Operator op2;
    if (immediate) {
        op1 = cond1.isUNSIGNED() ? PPC_CMPLI : PPC_CMPI;
        op2 = cond2.isUNSIGNED() ? PPC_CMPLI : PPC_CMPI;
    } else {
        op1 = cond1.isUNSIGNED() ? PPC_CMPL : PPC_CMP;
        op2 = cond2.isUNSIGNED() ? PPC_CMPL : PPC_CMP;
    }
    if (op1 == op2) {
        RegisterOperand cr = regpool.makeTempCondition();
        EMIT(MIR_Binary.create(op1, cr, val1, val2));
        EMIT(MIR_CondBranch2.mutate(s, PPC_BCOND2, cr.copyD2U(), new PowerPCConditionOperand(cond1), IfCmp2.getTarget1(s), IfCmp2.getBranchProfile1(s), new PowerPCConditionOperand(cond2), IfCmp2.getTarget2(s), IfCmp2.getBranchProfile2(s)));
    } else {
        RegisterOperand cr1 = regpool.makeTempCondition();
        RegisterOperand cr2 = regpool.makeTempCondition();
        EMIT(MIR_Binary.create(op1, cr1, val1, val2));
        EMIT(MIR_Binary.create(op2, cr2, val1, val2));
        EMIT(MIR_CondBranch.create(PPC_BCOND, cr1.copyD2U(), new PowerPCConditionOperand(cond1), IfCmp2.getTarget1(s), IfCmp2.getBranchProfile1(s)));
        EMIT(MIR_CondBranch.mutate(s, PPC_BCOND, cr2.copyD2U(), new PowerPCConditionOperand(cond2), IfCmp2.getTarget2(s), IfCmp2.getBranchProfile2(s)));
    }
}

Example 2 with PowerPCConditionOperand

use of org.jikesrvm.compilers.opt.ir.operand.ppc.PowerPCConditionOperand in project JikesRVM by JikesRVM.

the class ComplexLIR2MIRExpansion method threeValueCmp.

/**
 * compare to values and set result to -1, 0, 1 for <, =, >, respectively
 * @param s the compare instruction
 * @param ir the governing IR
 */
private static void threeValueCmp(Instruction s, IR ir) {
    PowerPCConditionOperand firstCond = PowerPCConditionOperand.LESS_EQUAL();
    int firstConst = 1;
    switch(s.getOpcode()) {
        case DOUBLE_CMPG_opcode:
        case FLOAT_CMPG_opcode:
            firstCond = PowerPCConditionOperand.GREATER_EQUAL();
            firstConst = -1;
            break;
        case DOUBLE_CMPL_opcode:
        case FLOAT_CMPL_opcode:
            break;
        default:
            if (VM.VerifyAssertions)
                VM._assert(VM.NOT_REACHED);
            break;
    }
    Register res = Binary.getClearResult(s).getRegister();
    RegisterOperand one = (RegisterOperand) Binary.getClearVal1(s);
    RegisterOperand two = (RegisterOperand) Binary.getClearVal2(s);
    res.setSpansBasicBlock();
    BasicBlock BB1 = s.getBasicBlock();
    BasicBlock BB6 = BB1.splitNodeAt(s, ir);
    s = s.remove();
    BasicBlock BB2 = BB1.createSubBlock(0, ir);
    BasicBlock BB3 = BB1.createSubBlock(0, ir);
    BasicBlock BB4 = BB1.createSubBlock(0, ir);
    BasicBlock BB5 = BB1.createSubBlock(0, ir);
    RegisterOperand t = ir.regpool.makeTempInt();
    t.getRegister().setCondition();
    BB1.appendInstruction(MIR_Binary.create(PPC_FCMPU, t, one, two));
    BB1.appendInstruction(MIR_CondBranch.create(PPC_BCOND, t.copyD2U(), firstCond, BB3.makeJumpTarget(), new BranchProfileOperand(0.5f)));
    BB2.appendInstruction(MIR_Unary.create(PPC_LDI, I(res), IC(firstConst)));
    BB2.appendInstruction(MIR_Branch.create(PPC_B, BB6.makeJumpTarget()));
    BB3.appendInstruction(MIR_CondBranch.create(PPC_BCOND, t.copyD2U(), PowerPCConditionOperand.EQUAL(), BB5.makeJumpTarget(), BranchProfileOperand.unlikely()));
    BB4.appendInstruction(MIR_Unary.create(PPC_LDI, I(res), IC(-firstConst)));
    BB4.appendInstruction(MIR_Branch.create(PPC_B, BB6.makeJumpTarget()));
    BB5.appendInstruction(MIR_Unary.create(PPC_LDI, I(res), IC(0)));
    // fix CFG
    BB1.insertOut(BB2);
    BB1.insertOut(BB3);
    BB2.insertOut(BB6);
    BB3.insertOut(BB4);
    BB3.insertOut(BB5);
    BB4.insertOut(BB6);
    BB5.insertOut(BB6);
    ir.cfg.linkInCodeOrder(BB1, BB2);
    ir.cfg.linkInCodeOrder(BB2, BB3);
    ir.cfg.linkInCodeOrder(BB3, BB4);
    ir.cfg.linkInCodeOrder(BB4, BB5);
    ir.cfg.linkInCodeOrder(BB5, BB6);
}

Example 3 with PowerPCConditionOperand

use of org.jikesrvm.compilers.opt.ir.operand.ppc.PowerPCConditionOperand in project JikesRVM by JikesRVM.

the class BURS_Helpers method CMP.

/**
 * emit basic code to handle an INT_IFCMP when no folding
 * of the compare into some other computation is possible.
 */
protected final void CMP(Instruction s, RegisterOperand val1, Operand val2, ConditionOperand cond, boolean immediate) {
    RegisterOperand cr = regpool.makeTempCondition();
    Operator op;
    if (immediate) {
        op = cond.isUNSIGNED() ? PPC_CMPLI : PPC_CMPI;
    } else {
        op = cond.isUNSIGNED() ? PPC_CMPL : PPC_CMP;
    }
    EMIT(MIR_Binary.create(op, cr, val1, val2));
    EMIT(MIR_CondBranch.mutate(s, PPC_BCOND, cr.copyD2U(), new PowerPCConditionOperand(cond), IfCmp.getTarget(s), IfCmp.getBranchProfile(s)));
}

Example 4 with PowerPCConditionOperand

use of org.jikesrvm.compilers.opt.ir.operand.ppc.PowerPCConditionOperand in project JikesRVM by JikesRVM.

the class BURS_Helpers method CMP64.

/**
 * emit basic code to handle an INT_IFCMP when no folding
 * of the compare into some other computation is possible.
 */
protected final void CMP64(Instruction s, RegisterOperand val1, Operand val2, ConditionOperand cond, boolean immediate) {
    if (VM.VerifyAssertions)
        VM._assert(VM.BuildFor64Addr);
    RegisterOperand cr = regpool.makeTempCondition();
    Operator op;
    if (immediate) {
        op = cond.isUNSIGNED() ? PPC64_CMPLI : PPC64_CMPI;
    } else {
        op = cond.isUNSIGNED() ? PPC64_CMPL : PPC64_CMP;
    }
    EMIT(MIR_Binary.create(op, cr, val1, val2));
    EMIT(MIR_CondBranch.mutate(s, PPC_BCOND, cr.copyD2U(), new PowerPCConditionOperand(cond), IfCmp.getTarget(s), IfCmp.getBranchProfile(s)));
}

Example 5 with PowerPCConditionOperand

use of org.jikesrvm.compilers.opt.ir.operand.ppc.PowerPCConditionOperand in project JikesRVM by JikesRVM.

the class BURS_Helpers method CMP_ZERO_AND_MASK.

protected final void CMP_ZERO_AND_MASK(Instruction s, RegisterOperand def, RegisterOperand left, IntConstantOperand Mask, ConditionOperand cond) {
    if (VM.VerifyAssertions)
        VM._assert(!cond.isUNSIGNED());
    int mask = Mask.value;
    if (mask < 0) {
        mask = ~mask;
        int MB = MaskBegin(mask);
        int ME = MaskEnd(mask);
        EMIT(MIR_RotateAndMask.create(PPC_RLWINMr, def, left, IC(0), IC((ME + 1) & 0x1f), IC(MB - 1)));
    } else {
        int MB = MaskBegin(mask);
        int ME = MaskEnd(mask);
        EMIT(MIR_RotateAndMask.create(PPC_RLWINMr, def, left, IC(0), IC(MB), IC(ME)));
    }
    EMIT(MIR_CondBranch.mutate(s, PPC_BCOND, CR(0), new PowerPCConditionOperand(cond), IfCmp.getTarget(s), IfCmp.getBranchProfile(s)));
}