use of com.cburch.logisim.circuit.Splitter in project logisim-evolution by reds-heig.
the class SimpleDRCContainer method ClearMarks.
public void ClearMarks() {
if (!DRCInfoPresent())
return;
for (Object obj : DRCComponents) {
if (obj instanceof Wire) {
Wire wire = (Wire) obj;
if ((MarkType & MARK_WIRE) != 0) {
wire.SetMarked(false);
}
} else if (obj instanceof Splitter) {
Splitter split = (Splitter) obj;
if ((MarkType & MARK_INSTANCE) != 0) {
split.SetMarked(false);
}
} else if (obj instanceof InstanceComponent) {
InstanceComponent comp = (InstanceComponent) obj;
comp.clearMarks();
}
}
}
use of com.cburch.logisim.circuit.Splitter in project logisim-evolution by reds-heig.
the class PortHDLGeneratorFactory method GetEntity.
// #2
@Override
public ArrayList<String> GetEntity(Netlist TheNetlist, AttributeSet attrs, String ComponentName, FPGAReport Reporter, String HDLType) {
NetlistComponent ComponentInfo = null;
compMap.put(ComponentName, new HashMap<Integer, InOutMap>());
for (NetlistComponent comp : TheNetlist.GetNormalComponents()) {
if (comp.GetComponent().getAttributeSet().equals(attrs)) {
ComponentInfo = comp;
break;
}
}
int mapIdx = 0;
for (int portNr = 0; portNr < ComponentInfo.GetComponent().getEnds().size(); portNr++) {
Location splitterLoc = findEndConnection(ComponentInfo.GetComponent().getEnd(portNr).getLocation(), TheNetlist.getCircuit());
if (splitterLoc == null) {
Reporter.AddFatalError("Found 0, 2 or more connections on PortIO's splitter (" + ComponentName + ")");
return null;
}
for (Splitter split : TheNetlist.getSplitters()) {
if (split.getLocation().equals(splitterLoc)) {
// trouve le
// premier
// splitter du
// Port
compMap.get(ComponentName).put(mapIdx, new InOutMap(Type.INOUT, new Point(0, split.GetEndpoints().length - 1), portNr));
int splitPortNr = 0;
for (EndData end : split.getEnds()) {
if (!end.getLocation().equals(splitterLoc)) {
// parcours
// les
// sortie
// du
// splitter
Location compLoc = findEndConnection(end.getLocation(), TheNetlist.getCircuit());
if (compLoc == null) {
Reporter.AddFatalError("Found 0, 2 or more connections on PortIO's splitter (" + ComponentName + ")");
return null;
}
for (Component comp : TheNetlist.getCircuit().getNonWires(compLoc)) {
// splitter
for (EndData port : comp.getEnds()) {
if (port.getLocation().equals(compLoc)) {
// splitter
if (!(comp instanceof Splitter) && !(comp instanceof PortIO)) {
if (port.isInput()) {
compMap.get(ComponentName).put(mapIdx, new InOutMap(Type.OUT, getBitRange(split.GetEndpoints(), splitPortNr), portNr));
} else if (port.isOutput()) {
compMap.get(ComponentName).put(mapIdx, new InOutMap(Type.IN, getBitRange(split.GetEndpoints(), splitPortNr), portNr));
}
} else {
Reporter.AddFatalError("Cannot connect PortIO's splitter to other splitter or PortIO (" + ComponentName + ")");
return null;
}
}
}
}
}
mapIdx++;
splitPortNr++;
}
}
}
}
ArrayList<String> Contents = new ArrayList<String>();
Contents.addAll(FileWriter.getGenerateRemark(ComponentName, VHDL, TheNetlist.projName()));
Contents.addAll(FileWriter.getExtendedLibrary());
Contents.add("ENTITY " + ComponentName + " IS");
Contents.add(" PORT ( ");
for (int i = 0; i < compMap.get(ComponentName).size(); i++) {
String line = " ";
switch(compMap.get(ComponentName).get(i).getType()) {
case IN:
line += inBusName + "_" + i + " : IN ";
break;
case OUT:
line += outBusName + "_" + i + " : OUT ";
break;
case INOUT:
line += inOutBusName + "_" + i + " : INOUT ";
break;
default:
Reporter.AddFatalError("Found component of unknown type (" + compMap.get(ComponentName).get(i).toString() + ")");
}
if (compMap.get(ComponentName).get(i).getSize() == 1) {
line += "std_logic";
} else {
line += "std_logic_vector (" + (compMap.get(ComponentName).get(i).getSize() - 1) + " DOWNTO 0)";
}
if (i == (compMap.get(ComponentName).size() - 1)) {
line += ")";
}
line += ";";
Contents.add(line);
}
Contents.add("END " + ComponentName + ";");
Contents.add("");
return Contents;
}
Aggregations