use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class LoadedLibrary method createAttributes.
private static AttributeSet createAttributes(ComponentFactory factory, AttributeSet src) {
AttributeSet dest = factory.createAttributeSet();
copyAttributes(dest, src);
return dest;
}
use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class LoadedLibrary method replaceAll.
private static void replaceAll(Circuit circuit, Map<ComponentFactory, ComponentFactory> compMap) {
ArrayList<Component> toReplace = null;
for (Component comp : circuit.getNonWires()) {
if (compMap.containsKey(comp.getFactory())) {
if (toReplace == null)
toReplace = new ArrayList<Component>();
toReplace.add(comp);
}
}
if (toReplace != null) {
CircuitMutation xn = new CircuitMutation(circuit);
for (Component comp : toReplace) {
xn.remove(comp);
ComponentFactory factory = compMap.get(comp.getFactory());
if (factory != null) {
AttributeSet newAttrs = createAttributes(factory, comp.getAttributeSet());
xn.add(factory.createComponent(comp.getLocation(), newAttrs));
}
}
xn.execute();
}
}
use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class SubcircuitFactory method drawCircuitLabel.
private void drawCircuitLabel(InstancePainter painter, Bounds bds, Direction facing, Direction defaultFacing) {
AttributeSet staticAttrs = source.getStaticAttributes();
String label = staticAttrs.getValue(CircuitAttributes.CIRCUIT_LABEL_ATTR);
if (label != null && !label.equals("")) {
Direction up = staticAttrs.getValue(CircuitAttributes.CIRCUIT_LABEL_FACING_ATTR);
Font font = staticAttrs.getValue(CircuitAttributes.CIRCUIT_LABEL_FONT_ATTR);
int back = label.indexOf('\\');
int lines = 1;
boolean backs = false;
while (back >= 0 && back <= label.length() - 2) {
char c = label.charAt(back + 1);
if (c == 'n')
lines++;
else if (c == '\\')
backs = true;
back = label.indexOf('\\', back + 2);
}
int x = bds.getX() + bds.getWidth() / 2;
int y = bds.getY() + bds.getHeight() / 2;
Graphics g = painter.getGraphics().create();
double angle = Math.PI / 2 - (up.toRadians() - defaultFacing.toRadians()) - facing.toRadians();
if (g instanceof Graphics2D && Math.abs(angle) > 0.01) {
Graphics2D g2 = (Graphics2D) g;
g2.rotate(angle, x, y);
}
g.setFont(font);
if (lines == 1 && !backs) {
GraphicsUtil.drawCenteredText(g, label, x, y);
} else {
FontMetrics fm = g.getFontMetrics();
int height = fm.getHeight();
y = y - (height * lines - fm.getLeading()) / 2 + fm.getAscent();
back = label.indexOf('\\');
while (back >= 0 && back <= label.length() - 2) {
char c = label.charAt(back + 1);
if (c == 'n') {
String line = label.substring(0, back);
GraphicsUtil.drawText(g, line, x, y, GraphicsUtil.H_CENTER, GraphicsUtil.V_BASELINE);
y += height;
label = label.substring(back + 2);
back = label.indexOf('\\');
} else if (c == '\\') {
label = label.substring(0, back) + label.substring(back + 1);
back = label.indexOf('\\', back + 1);
} else {
back = label.indexOf('\\', back + 2);
}
}
GraphicsUtil.drawText(g, label, x, y, GraphicsUtil.H_CENTER, GraphicsUtil.V_BASELINE);
}
g.dispose();
}
}
use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class ShiftRegisterHDLGeneratorFactory method GetPortMap.
@Override
public SortedMap<String, String> GetPortMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter, String HDLType) {
SortedMap<String, String> PortMap = new TreeMap<String, String>();
Boolean GatedClock = false;
Boolean HasClock = true;
Boolean ActiveLow = false;
String ZeroBit = (HDLType.equals(VHDL)) ? "'0'" : "1'b0";
String SetBit = (HDLType.equals(VHDL)) ? "'1'" : "1'b1";
String BracketOpen = (HDLType.equals(VHDL)) ? "(" : "[";
String BracketClose = (HDLType.equals(VHDL)) ? ")" : "]";
AttributeSet attrs = ComponentInfo.GetComponent().getAttributeSet();
int NrOfBits = attrs.getValue(StdAttr.WIDTH).getWidth();
int NrOfStages = attrs.getValue(ShiftRegister.ATTR_LENGTH);
if (!ComponentInfo.EndIsConnected(ShiftRegister.CK)) {
Reporter.AddSevereWarning("Component \"Shift Register\" in circuit \"" + Nets.getCircuitName() + "\" has no clock connection");
HasClock = false;
}
String ClockNetName = GetClockNetName(ComponentInfo, ShiftRegister.CK, Nets);
GatedClock = ClockNetName.isEmpty();
ActiveLow = attrs.getValue(StdAttr.EDGE_TRIGGER) == StdAttr.TRIG_FALLING;
Boolean HasParallelLoad = attrs.getValue(ShiftRegister.ATTR_LOAD).booleanValue();
PortMap.putAll(GetNetMap("Reset", true, ComponentInfo, ShiftRegister.CLR, Reporter, HDLType, Nets));
if (HasClock && !GatedClock) {
if (Nets.RequiresGlobalClockConnection()) {
PortMap.put("Tick", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.GlobalClockIndex) + BracketClose);
} else {
if (ActiveLow)
PortMap.put("Tick", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.NegativeEdgeTickIndex) + BracketClose);
else
PortMap.put("Tick", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.PositiveEdgeTickIndex) + BracketClose);
}
PortMap.put("Clock", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.GlobalClockIndex) + BracketClose);
} else if (!HasClock) {
PortMap.put("Tick", ZeroBit);
PortMap.put("Clock", ZeroBit);
} else {
PortMap.put("Tick", SetBit);
if (!GatedClock) {
if (ActiveLow)
PortMap.put("Clock", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.InvertedDerivedClockIndex) + BracketClose);
else
PortMap.put("Clock", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.DerivedClockIndex) + BracketClose);
} else {
PortMap.put("Clock", GetNetName(ComponentInfo, ShiftRegister.CK, true, HDLType, Nets));
}
}
PortMap.putAll(GetNetMap("ShiftEnable", false, ComponentInfo, ShiftRegister.SH, Reporter, HDLType, Nets));
if (HasParallelLoad) {
PortMap.putAll(GetNetMap("ParLoad", true, ComponentInfo, ShiftRegister.LD, Reporter, HDLType, Nets));
} else {
PortMap.put("ParLoad", ZeroBit);
}
String ShiftName = "ShiftIn";
if (HDLType.equals(VHDL) & (NrOfBits == 1))
ShiftName += "(0)";
PortMap.putAll(GetNetMap(ShiftName, true, ComponentInfo, ShiftRegister.IN, Reporter, HDLType, Nets));
if (HasParallelLoad) {
StringBuffer Vector = new StringBuffer();
if (NrOfBits == 1) {
if (HDLType.equals(VHDL)) {
for (int i = 0; i < NrOfStages; i++) {
PortMap.putAll(GetNetMap("D" + BracketOpen + Integer.toString(i) + BracketClose, true, ComponentInfo, 6 + 2 * i, Reporter, HDLType, Nets));
}
for (int i = 0; i < NrOfStages - 1; i++) {
PortMap.putAll(GetNetMap("Q" + BracketOpen + Integer.toString(i) + BracketClose, true, ComponentInfo, 7 + 2 * i, Reporter, HDLType, Nets));
PortMap.put("Q" + BracketOpen + Integer.toString(NrOfStages - 1) + BracketClose, "OPEN");
}
} else {
for (int i = 0; i < NrOfStages; i++) {
if (Vector.length() != 0)
Vector.append(",");
Vector.append(GetNetName(ComponentInfo, 6 + 2 * i, true, HDLType, Nets));
}
PortMap.put("D", Vector.toString());
Vector.setLength(0);
for (int i = 0; i < NrOfStages - 1; i++) {
if (Vector.length() != 0)
Vector.append(",");
Vector.append(GetNetName(ComponentInfo, 7 + 2 * i, true, HDLType, Nets));
}
Vector.append(", ");
PortMap.put("Q", Vector.toString());
}
} else {
if (HDLType.equals(VHDL)) {
for (int bit = 0; bit < NrOfBits; bit++) {
for (int i = 0; i < NrOfStages; i++) {
PortMap.put("D" + BracketOpen + Integer.toString(bit * NrOfStages + i) + BracketClose, GetBusEntryName(ComponentInfo, 6 + 2 * i, true, bit, HDLType, Nets));
}
}
for (int bit = 0; bit < NrOfBits; bit++) {
for (int i = 0; i < NrOfStages - 1; i++) {
PortMap.put("Q" + BracketOpen + Integer.toString(bit * NrOfStages + i) + BracketClose, GetBusEntryName(ComponentInfo, 7 + 2 * i, true, bit, HDLType, Nets));
}
PortMap.put("Q" + BracketOpen + Integer.toString((bit + 1) * NrOfStages - 1) + BracketClose, "OPEN");
}
} else {
Vector.setLength(0);
for (int bit = 0; bit < NrOfBits; bit++) {
for (int i = 0; i < NrOfStages; i++) {
if (Vector.length() != 0)
Vector.append(",");
Vector.append(GetBusEntryName(ComponentInfo, 6 + 2 * i, true, bit, HDLType, Nets));
}
}
PortMap.put("D", Vector.toString());
Vector.setLength(0);
for (int bit = 0; bit < NrOfBits; bit++) {
for (int i = 0; i < NrOfStages - 1; i++) {
if (Vector.length() != 0)
Vector.append(",");
Vector.append(GetBusEntryName(ComponentInfo, 7 + 2 * i, true, bit, HDLType, Nets));
}
Vector.append(", ");
}
PortMap.put("Q", Vector.toString());
}
}
} else {
PortMap.put("Q", (HDLType.equals(VHDL)) ? "OPEN" : "");
StringBuffer Temp = new StringBuffer();
if (HDLType.equals(VERILOG)) {
Temp.append("0");
} else {
Temp.append("\"");
for (int i = 0; i < NrOfBits * NrOfStages; i++) Temp.append("0");
Temp.append("\"");
}
PortMap.put("D", Temp.toString());
}
String ShiftOut = "ShiftOut";
if (HDLType.equals(VHDL) & (NrOfBits == 1))
ShiftOut += "(0)";
PortMap.putAll(GetNetMap(ShiftOut, true, ComponentInfo, ShiftRegister.OUT, Reporter, HDLType, Nets));
return PortMap;
}
use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.
the class Clock method tick.
//
// package methods
//
public static boolean tick(CircuitState circState, int ticks, Component comp) {
AttributeSet attrs = comp.getAttributeSet();
int durationHigh = attrs.getValue(ATTR_HIGH).intValue();
int durationLow = attrs.getValue(ATTR_LOW).intValue();
ClockState state = (ClockState) circState.getData(comp);
if (state == null) {
state = new ClockState();
circState.setData(comp, state);
}
boolean curValue = ticks % (durationHigh + durationLow) < durationLow;
if (state.clicks % 2 == 1) {
curValue = !curValue;
}
Value desired = (curValue ? Value.FALSE : Value.TRUE);
if (!state.sending.equals(desired)) {
state.sending = desired;
Instance.getInstanceFor(comp).fireInvalidated();
return true;
} else {
return false;
}
}
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