Examples with AttributeSet com.cburch.logisim.data.AttributeSet used on opensource projects

Example 16 with AttributeSet

use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.

the class RegisterHDLGeneratorFactory method GetPortMap.

@Override
public SortedMap<String, String> GetPortMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter, String HDLType) {
    SortedMap<String, String> PortMap = new TreeMap<String, String>();
    Boolean GatedClock = false;
    Boolean HasClock = true;
    Boolean ActiveLow = false;
    String ZeroBit = (HDLType.equals(VHDL)) ? "'0'" : "1'b0";
    String SetBit = (HDLType.equals(VHDL)) ? "'1'" : "1'b1";
    String BracketOpen = (HDLType.equals(VHDL)) ? "(" : "[";
    String BracketClose = (HDLType.equals(VHDL)) ? ")" : "]";
    AttributeSet attrs = ComponentInfo.GetComponent().getAttributeSet();
    if (!ComponentInfo.EndIsConnected(Register.CK)) {
        Reporter.AddSevereWarning("Component \"Register\" in circuit \"" + Nets.getCircuitName() + "\" has no clock connection");
        HasClock = false;
    }
    String ClockNetName = GetClockNetName(ComponentInfo, Register.CK, Nets);
    if (ClockNetName.isEmpty()) {
        GatedClock = true;
    }
    if (attrs.getValue(StdAttr.TRIGGER) == StdAttr.TRIG_FALLING || attrs.getValue(StdAttr.TRIGGER) == StdAttr.TRIG_LOW)
        ActiveLow = true;
    PortMap.putAll(GetNetMap("Reset", true, ComponentInfo, Register.CLR, Reporter, HDLType, Nets));
    PortMap.putAll(GetNetMap("ClockEnable", false, ComponentInfo, Register.EN, Reporter, HDLType, Nets));
    if (HasClock && !GatedClock && Netlist.IsFlipFlop(attrs)) {
        if (Nets.RequiresGlobalClockConnection()) {
            PortMap.put("Tick", SetBit);
        } else {
            if (ActiveLow)
                PortMap.put("Tick", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.NegativeEdgeTickIndex) + BracketClose);
            else
                PortMap.put("Tick", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.PositiveEdgeTickIndex) + BracketClose);
        }
        PortMap.put("Clock", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.GlobalClockIndex) + BracketClose);
    } else if (!HasClock) {
        PortMap.put("Tick", ZeroBit);
        PortMap.put("Clock", ZeroBit);
    } else {
        PortMap.put("Tick", SetBit);
        if (!GatedClock) {
            if (ActiveLow)
                PortMap.put("Clock", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.InvertedDerivedClockIndex) + BracketClose);
            else
                PortMap.put("Clock", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.DerivedClockIndex) + BracketClose);
        } else {
            PortMap.put("Clock", GetNetName(ComponentInfo, Register.CK, true, HDLType, Nets));
        }
    }
    String Input = "D";
    String Output = "Q";
    if (HDLType.equals(VHDL) & (ComponentInfo.GetComponent().getAttributeSet().getValue(StdAttr.WIDTH).getWidth() == 1)) {
        Input += "(0)";
        Output += "(0)";
    }
    PortMap.putAll(GetNetMap(Input, true, ComponentInfo, Register.IN, Reporter, HDLType, Nets));
    PortMap.putAll(GetNetMap(Output, true, ComponentInfo, Register.OUT, Reporter, HDLType, Nets));
    return PortMap;
}

Example 17 with AttributeSet

use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.

the class RegisterHDLGeneratorFactory method GetParameterMap.

@Override
public SortedMap<String, Integer> GetParameterMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter) {
    SortedMap<String, Integer> ParameterMap = new TreeMap<String, Integer>();
    int ActiveLevel = 1;
    Boolean GatedClock = false;
    Boolean ActiveLow = false;
    AttributeSet attrs = ComponentInfo.GetComponent().getAttributeSet();
    String ClockNetName = GetClockNetName(ComponentInfo, Register.CK, Nets);
    if (ClockNetName.isEmpty()) {
        GatedClock = true;
        if (Netlist.IsFlipFlop(attrs))
            Reporter.AddWarning("Found a gated clock for component \"Register\" in circuit \"" + Nets.getCircuitName() + "\"");
    }
    if (attrs.getValue(StdAttr.TRIGGER) == StdAttr.TRIG_FALLING || attrs.getValue(StdAttr.TRIGGER) == StdAttr.TRIG_LOW)
        ActiveLow = true;
    if (GatedClock && ActiveLow) {
        ActiveLevel = 0;
    }
    ParameterMap.put(ActiveLevelStr, ActiveLevel);
    ParameterMap.put(NrOfBitsStr, ComponentInfo.GetComponent().getEnd(Register.IN).getWidth().getWidth());
    return ParameterMap;
}

Example 18 with AttributeSet

use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.

the class Rom method DrawControlBlock.

private void DrawControlBlock(InstancePainter painter, int xpos, int ypos) {
    Graphics g = painter.getGraphics();
    GraphicsUtil.switchToWidth(g, 2);
    AttributeSet attrs = painter.getAttributeSet();
    g.drawLine(xpos + 20, ypos, xpos + 20 + SymbolWidth, ypos);
    g.drawLine(xpos + 20, ypos, xpos + 20, ypos + getControlHeight(attrs) - 10);
    g.drawLine(xpos + 20 + SymbolWidth, ypos, xpos + 20 + SymbolWidth, ypos + getControlHeight(attrs) - 10);
    g.drawLine(xpos + 20, ypos + getControlHeight(attrs) - 10, xpos + 30, ypos + getControlHeight(attrs) - 10);
    g.drawLine(xpos + 20 + SymbolWidth - 10, ypos + getControlHeight(attrs) - 10, xpos + 20 + SymbolWidth, ypos + getControlHeight(attrs) - 10);
    g.drawLine(xpos + 30, ypos + getControlHeight(attrs) - 10, xpos + 30, ypos + getControlHeight(attrs));
    g.drawLine(xpos + 20 + SymbolWidth - 10, ypos + getControlHeight(attrs) - 10, xpos + 20 + SymbolWidth - 10, ypos + getControlHeight(attrs));
    GraphicsUtil.drawCenteredText(g, "ROM " + GetSizeLabel(painter.getAttributeValue(Mem.ADDR_ATTR).getWidth()) + " x " + Integer.toString(painter.getAttributeValue(Mem.DATA_ATTR).getWidth()), xpos + (SymbolWidth / 2) + 20, ypos + 5);
    GraphicsUtil.switchToWidth(g, 1);
    DrawAddress(painter, xpos, ypos + 10, painter.getAttributeValue(Mem.ADDR_ATTR).getWidth());
}

Example 19 with AttributeSet

use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.

the class RamHDLGeneratorFactory method GetPortMap.

@Override
public SortedMap<String, String> GetPortMap(Netlist Nets, NetlistComponent ComponentInfo, FPGAReport Reporter, String HDLType) {
    AttributeSet attrs = ComponentInfo.GetComponent().getAttributeSet();
    SortedMap<String, String> PortMap = new TreeMap<String, String>();
    Object trigger = attrs.getValue(StdAttr.TRIGGER);
    boolean asynch = trigger.equals(StdAttr.TRIG_HIGH) || trigger.equals(StdAttr.TRIG_LOW);
    Object be = attrs.getValue(RamAttributes.ATTR_ByteEnables);
    boolean byteEnables = be == null ? false : be.equals(RamAttributes.BUS_WITH_BYTEENABLES);
    PortMap.putAll(GetNetMap("Address", true, ComponentInfo, Mem.ADDR, Reporter, HDLType, Nets));
    int DinPin = (asynch) ? Ram.ADIN : Ram.SDIN;
    PortMap.putAll(GetNetMap("DataIn", true, ComponentInfo, DinPin, Reporter, HDLType, Nets));
    PortMap.putAll(GetNetMap("WE", true, ComponentInfo, Ram.WE, Reporter, HDLType, Nets));
    PortMap.putAll(GetNetMap("OE", true, ComponentInfo, Ram.OE, Reporter, HDLType, Nets));
    if (!asynch) {
        String SetBit = (HDLType.equals(VHDL)) ? "'1'" : "1'b1";
        String ZeroBit = (HDLType.equals(VHDL)) ? "'0'" : "1'b0";
        String BracketOpen = (HDLType.equals(VHDL)) ? "(" : "[";
        String BracketClose = (HDLType.equals(VHDL)) ? ")" : "]";
        if (!ComponentInfo.EndIsConnected(Ram.CLK)) {
            Reporter.AddError("Component \"RAM\" in circuit \"" + Nets.getCircuitName() + "\" has no clock connection!");
            PortMap.put("Clock", ZeroBit);
            PortMap.put("Tick", ZeroBit);
        } else {
            String ClockNetName = GetClockNetName(ComponentInfo, Ram.CLK, Nets);
            if (ClockNetName.isEmpty()) {
                PortMap.putAll(GetNetMap("Clock", true, ComponentInfo, Ram.CLK, Reporter, HDLType, Nets));
                PortMap.put("Tick", SetBit);
            } else {
                int ClockBusIndex;
                if (Nets.RequiresGlobalClockConnection()) {
                    ClockBusIndex = ClockHDLGeneratorFactory.GlobalClockIndex;
                } else {
                    ClockBusIndex = (attrs.getValue(StdAttr.TRIGGER) == StdAttr.TRIG_RISING) ? ClockHDLGeneratorFactory.PositiveEdgeTickIndex : ClockHDLGeneratorFactory.NegativeEdgeTickIndex;
                }
                PortMap.put("Clock", ClockNetName + BracketOpen + Integer.toString(ClockHDLGeneratorFactory.GlobalClockIndex) + BracketClose);
                PortMap.put("Tick", ClockNetName + BracketOpen + Integer.toString(ClockBusIndex) + BracketClose);
            }
        }
    }
    if (byteEnables) {
        int NrOfByteEnables = Ram.GetNrOfByteEnables(ComponentInfo.GetComponent().getAttributeSet());
        int ByteEnableOffset = Ram.ByteEnableIndex(ComponentInfo.GetComponent().getAttributeSet());
        for (int i = 0; i < NrOfByteEnables; i++) {
            PortMap.putAll(GetNetMap("ByteEnable" + Integer.toString(i), false, ComponentInfo, ByteEnableOffset + NrOfByteEnables - i - 1, Reporter, HDLType, Nets));
        }
    }
    PortMap.putAll(GetNetMap("DataOut", true, ComponentInfo, Mem.DATA, Reporter, HDLType, Nets));
    return PortMap;
}

Example 20 with AttributeSet

use of com.cburch.logisim.data.AttributeSet in project logisim-evolution by reds-heig.

the class Circuit method RemoveWrongLabels.

private void RemoveWrongLabels(String Label) {
    boolean HaveAChange = false;
    for (Component comp : comps) {
        AttributeSet attrs = comp.getAttributeSet();
        if (attrs.containsAttribute(StdAttr.LABEL)) {
            String CompLabel = attrs.getValue(StdAttr.LABEL);
            if (Label.toUpperCase().equals(CompLabel.toUpperCase())) {
                attrs.setValue(StdAttr.LABEL, "");
                HaveAChange = true;
            }
        }
    }
    /* we do not have to check the wires as (1) Wire is a reserved keyword, and (2) they cannot have a label */
    if (HaveAChange)
        JOptionPane.showMessageDialog(null, "\"" + Label + "\" : " + Strings.get("ComponentLabelCollisionError"));
}