Examples with Register org.jikesrvm.compilers.opt.ir.Register used on opensource projects

Example 21 with Register

use of org.jikesrvm.compilers.opt.ir.Register in project JikesRVM by JikesRVM.

the class BURS_Helpers method LONG_USHR_IMM.

protected final void LONG_USHR_IMM(Instruction s, RegisterOperand def, RegisterOperand left, IntConstantOperand right) {
    if (VM.VerifyAssertions)
        VM._assert(VM.BuildFor32Addr);
    Register defHigh = def.getRegister();
    Register defLow = regpool.getSecondReg(defHigh);
    Register leftHigh = left.getRegister();
    Register leftLow = regpool.getSecondReg(leftHigh);
    int shift = right.value;
    if (shift < 32) {
        EMIT(MIR_RotateAndMask.create(PPC_RLWINM, I(defLow), I(leftLow), IC(32 - shift), IC(shift), IC(31)));
        EMIT(MIR_RotateAndMask.create(PPC_RLWIMI, I(defLow), I(defLow), I(leftHigh), IC(32 - shift), IC(0), IC(shift - 1)));
        EMIT(MIR_RotateAndMask.create(PPC_RLWINM, I(defHigh), I(leftHigh), IC(32 - shift), IC(shift), IC(31)));
    } else if (shift == 32) {
        EMIT(MIR_Move.create(PPC_MOVE, I(defLow), I(leftHigh)));
        EMIT(MIR_Unary.create(PPC_LDI, I(defHigh), IC(0)));
    } else if (shift < 64) {
        shift = shift - 32;
        EMIT(MIR_Binary.create(PPC_SRWI, I(defLow), I(leftHigh), IC(shift)));
        EMIT(MIR_Unary.create(PPC_LDI, I(defHigh), IC(0)));
    } else {
        EMIT(MIR_Unary.create(PPC_LDI, I(defHigh), IC(0)));
        EMIT(MIR_Unary.create(PPC_LDI, I(defLow), IC(0)));
    }
}

Example 22 with Register

use of org.jikesrvm.compilers.opt.ir.Register in project JikesRVM by JikesRVM.

the class BURS_Helpers method LONG_STORE_addi.

protected final void LONG_STORE_addi(Instruction s, RegisterOperand def, RegisterOperand left, IntConstantOperand right, LocationOperand loc, Operand guard) {
    if (VM.VerifyAssertions)
        VM._assert(VM.BuildFor32Addr);
    Register defHigh = def.getRegister();
    Register defLow = regpool.getSecondReg(defHigh);
    int imm = right.value;
    if (VM.VerifyAssertions) {
        VM._assert(imm < (0x8000 - 4));
    }
    Instruction inst = MIR_Store.create(PPC_STW, I(defHigh), left, IC(imm), loc, guard);
    inst.copyPosition(s);
    EMIT(inst);
    if (loc != null) {
        loc = (LocationOperand) loc.copy();
    }
    if (guard != null) {
        guard = guard.copy();
    }
    inst = MIR_Store.create(PPC_STW, I(defLow), left.copyU2U(), IC(imm + 4), loc, guard);
    inst.copyPosition(s);
    EMIT(inst);
}

Example 23 with Register

use of org.jikesrvm.compilers.opt.ir.Register in project JikesRVM by JikesRVM.

the class BURS_Helpers method mutateTrapToCall.

private void mutateTrapToCall(Instruction s, RVMMethod target) {
    Offset offset = target.getOffset();
    RegisterOperand tmp = regpool.makeTemp(TypeReference.JavaLangObjectArray);
    Register JTOC = regpool.getPhysicalRegisterSet().asPPC().getJTOC();
    MethodOperand meth = MethodOperand.STATIC(target);
    meth.setIsNonReturningCall(true);
    int valueLow = PPCMaskLower16(offset);
    if (fits(offset, 16)) {
        EMIT(MIR_Load.create(PPC_LAddr, tmp, A(JTOC), IC(valueLow)));
    } else {
        int valueHigh = PPCMaskUpper16(offset);
        if (VM.VerifyAssertions)
            VM._assert(fits(offset, 32));
        Register reg = regpool.getAddress();
        EMIT(MIR_Binary.create(PPC_ADDIS, A(reg), A(JTOC), IC(valueHigh)));
        EMIT(MIR_Load.create(PPC_LAddr, tmp, A(reg), IC(valueLow)));
    }
    EMIT(MIR_Move.create(PPC_MTSPR, A(CTR), tmp.copyD2U()));
    EMIT(MIR_Call.mutate0(s, PPC_BCTRL, null, null, meth));
}

Example 24 with Register

use of org.jikesrvm.compilers.opt.ir.Register in project JikesRVM by JikesRVM.

the class ComplexLIR2MIRExpansion method boolean_cmp.

private static void boolean_cmp(Instruction s, IR ir, boolean cmp32Bit) {
    // undo the optimization because it cannot efficiently be generated
    Register res = BooleanCmp.getClearResult(s).getRegister();
    RegisterOperand one = (RegisterOperand) BooleanCmp.getClearVal1(s);
    Operand two = BooleanCmp.getClearVal2(s);
    ConditionOperand cond = BooleanCmp.getClearCond(s);
    res.setSpansBasicBlock();
    BasicBlock BB1 = s.getBasicBlock();
    BasicBlock BB4 = BB1.splitNodeAt(s, ir);
    s = s.remove();
    BasicBlock BB2 = BB1.createSubBlock(0, ir);
    BasicBlock BB3 = BB1.createSubBlock(0, ir);
    RegisterOperand t = ir.regpool.makeTempInt();
    t.getRegister().setCondition();
    Operator op;
    if (VM.BuildFor64Addr && !cmp32Bit) {
        if (two instanceof IntConstantOperand) {
            op = cond.isUNSIGNED() ? PPC64_CMPLI : PPC64_CMPI;
        } else {
            op = cond.isUNSIGNED() ? PPC64_CMPL : PPC64_CMP;
        }
    } else if (two instanceof IntConstantOperand) {
        op = cond.isUNSIGNED() ? PPC_CMPLI : PPC_CMPI;
    } else {
        op = cond.isUNSIGNED() ? PPC_CMPL : PPC_CMP;
    }
    BB1.appendInstruction(MIR_Binary.create(op, t, one, two));
    BB1.appendInstruction(MIR_CondBranch.create(PPC_BCOND, t.copyD2U(), PowerPCConditionOperand.get(cond), BB3.makeJumpTarget(), new BranchProfileOperand()));
    BB2.appendInstruction(MIR_Unary.create(PPC_LDI, I(res), IC(0)));
    BB2.appendInstruction(MIR_Branch.create(PPC_B, BB4.makeJumpTarget()));
    BB3.appendInstruction(MIR_Unary.create(PPC_LDI, I(res), IC(1)));
    // fix CFG
    BB1.insertOut(BB2);
    BB1.insertOut(BB3);
    BB2.insertOut(BB4);
    BB3.insertOut(BB4);
    ir.cfg.linkInCodeOrder(BB1, BB2);
    ir.cfg.linkInCodeOrder(BB2, BB3);
    ir.cfg.linkInCodeOrder(BB3, BB4);
}

Example 25 with Register

use of org.jikesrvm.compilers.opt.ir.Register in project JikesRVM by JikesRVM.

the class ComplexLIR2MIRExpansion method threeValueCmp.

/**
 * compare to values and set result to -1, 0, 1 for <, =, >, respectively
 * @param s the compare instruction
 * @param ir the governing IR
 */
private static void threeValueCmp(Instruction s, IR ir) {
    PowerPCConditionOperand firstCond = PowerPCConditionOperand.LESS_EQUAL();
    int firstConst = 1;
    switch(s.getOpcode()) {
        case DOUBLE_CMPG_opcode:
        case FLOAT_CMPG_opcode:
            firstCond = PowerPCConditionOperand.GREATER_EQUAL();
            firstConst = -1;
            break;
        case DOUBLE_CMPL_opcode:
        case FLOAT_CMPL_opcode:
            break;
        default:
            if (VM.VerifyAssertions)
                VM._assert(VM.NOT_REACHED);
            break;
    }
    Register res = Binary.getClearResult(s).getRegister();
    RegisterOperand one = (RegisterOperand) Binary.getClearVal1(s);
    RegisterOperand two = (RegisterOperand) Binary.getClearVal2(s);
    res.setSpansBasicBlock();
    BasicBlock BB1 = s.getBasicBlock();
    BasicBlock BB6 = BB1.splitNodeAt(s, ir);
    s = s.remove();
    BasicBlock BB2 = BB1.createSubBlock(0, ir);
    BasicBlock BB3 = BB1.createSubBlock(0, ir);
    BasicBlock BB4 = BB1.createSubBlock(0, ir);
    BasicBlock BB5 = BB1.createSubBlock(0, ir);
    RegisterOperand t = ir.regpool.makeTempInt();
    t.getRegister().setCondition();
    BB1.appendInstruction(MIR_Binary.create(PPC_FCMPU, t, one, two));
    BB1.appendInstruction(MIR_CondBranch.create(PPC_BCOND, t.copyD2U(), firstCond, BB3.makeJumpTarget(), new BranchProfileOperand(0.5f)));
    BB2.appendInstruction(MIR_Unary.create(PPC_LDI, I(res), IC(firstConst)));
    BB2.appendInstruction(MIR_Branch.create(PPC_B, BB6.makeJumpTarget()));
    BB3.appendInstruction(MIR_CondBranch.create(PPC_BCOND, t.copyD2U(), PowerPCConditionOperand.EQUAL(), BB5.makeJumpTarget(), BranchProfileOperand.unlikely()));
    BB4.appendInstruction(MIR_Unary.create(PPC_LDI, I(res), IC(-firstConst)));
    BB4.appendInstruction(MIR_Branch.create(PPC_B, BB6.makeJumpTarget()));
    BB5.appendInstruction(MIR_Unary.create(PPC_LDI, I(res), IC(0)));
    // fix CFG
    BB1.insertOut(BB2);
    BB1.insertOut(BB3);
    BB2.insertOut(BB6);
    BB3.insertOut(BB4);
    BB3.insertOut(BB5);
    BB4.insertOut(BB6);
    BB5.insertOut(BB6);
    ir.cfg.linkInCodeOrder(BB1, BB2);
    ir.cfg.linkInCodeOrder(BB2, BB3);
    ir.cfg.linkInCodeOrder(BB3, BB4);
    ir.cfg.linkInCodeOrder(BB4, BB5);
    ir.cfg.linkInCodeOrder(BB5, BB6);
}