Examples with Component com.cburch.logisim.comp.Component used on opensource projects

Example 71 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class VhdlSimulator method generateFiles.

public void generateFiles() {
    vhdlTop.fireInvalidated();
    tclRun.fireInvalidated();
    new File(SIM_PATH).mkdirs();
    new File(SIM_SRC_PATH).mkdirs();
    new File(SIM_COMP_PATH).mkdirs();
    try {
        Files.copy(this.getClass().getResourceAsStream(SIM_RESOURCES_PATH + "questasim_binder.tcl"), Paths.get(SIM_PATH + "questasim_binder.tcl"), StandardCopyOption.REPLACE_EXISTING);
        Files.copy(this.getClass().getResourceAsStream(SIM_RESOURCES_PATH + "run.tcl"), Paths.get(SIM_PATH + "run.tcl"), StandardCopyOption.REPLACE_EXISTING);
        Files.copy(this.getClass().getResourceAsStream(SIM_RESOURCES_PATH + "modelsim.ini"), Paths.get(SIM_COMP_PATH + "modelsim.ini"), StandardCopyOption.REPLACE_EXISTING);
    } catch (IOException e) {
        logger.error("Cannot copy simulation files: {}", e.getMessage());
        e.printStackTrace();
    }
    vhdlTop.generate();
    tclRun.generate();
    /* Generate each component's file */
    for (Component comp : getVhdlComponents(project.getCircuitState())) {
        ((VhdlEntity) comp.getFactory()).saveFile(comp.getAttributeSet());
    }
}

Example 72 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class VhdlSimulatorTclComp method generate.

public void generate() {
    /* Do not generate if file is already valid */
    if (valid)
        return;
    StringBuilder comp_files = new StringBuilder();
    comp_files.append("Autogenerated by logisim");
    comp_files.append(System.getProperty("line.separator"));
    /* For each vhdl entity */
    for (Component comp : VhdlSimulator.getVhdlComponents(vhdlSimulator.getProject().getCircuitState())) {
        if (comp.getFactory().getClass().equals(VhdlEntity.class)) {
            InstanceState state = vhdlSimulator.getProject().getCircuitState().getInstanceState(comp);
            String componentName = comp.getFactory().getHDLTopName(state.getInstance().getAttributeSet());
            comp_files.append("vcom -reportprogress 300 -work work ../src/" + componentName + ".vhdl");
            comp_files.append(System.getProperty("line.separator"));
        }
    }
    /*
		 * Replace template blocks by generated data
		 */
    String template;
    try {
        template = new String(FileUtil.getBytes(this.getClass().getResourceAsStream((VhdlSimulator.SIM_RESOURCES_PATH + "comp.templ"))));
        template = template.replaceAll("%date%", LocaleManager.parserSDF.format(new Date()));
        template = template.replaceAll("%comp_files%", comp_files.toString());
    } catch (IOException e) {
        logger.error("Could not read template : {}", e.getMessage());
        return;
    }
    PrintWriter writer;
    try {
        writer = new PrintWriter(VhdlSimulator.SIM_PATH + "comp.tcl", "UTF-8");
        writer.print(template);
        writer.close();
    } catch (FileNotFoundException e) {
        logger.error("Could not create run.tcl file : {}", e.getMessage());
        e.printStackTrace();
        return;
    } catch (UnsupportedEncodingException e) {
        logger.error("Could not create run.tcl file : {}", e.getMessage());
        e.printStackTrace();
        return;
    }
    valid = true;
}

Example 73 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class Netlist method WarningTraceForGatedClock.

private void WarningTraceForGatedClock(ConnectionPoint Source, int index, ArrayList<Netlist> HierarchyNetlists, ArrayList<String> HierarchyNames, FPGAReport Reporter) {
    Component comp = Source.GetComp();
    if (comp.getFactory() instanceof Pin) {
        if (HierarchyNames.isEmpty())
            /* we cannot go up at toplevel, so leave */
            return;
        int idx = -1;
        for (int i = 0; i < MyInputPorts.size(); i++) {
            if (MyInputPorts.get(i).GetComponent().equals(comp))
                idx = i;
        }
        if (idx < 0) {
            Reporter.AddFatalError("BUG: Could not find port!\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
            return;
        }
        ConnectionPoint SubNet = HierarchyNetlists.get(HierarchyNetlists.size() - 2).GetNetlistConnectionForSubCircuitInput(HierarchyNames.get(HierarchyNames.size() - 1), idx, (byte) index);
        if (SubNet == null) {
            Reporter.AddFatalError("BUG: Could not find a sub-circuit connection in overlying hierarchy level!\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
            return;
        }
        if (SubNet.GetParrentNet() != null) {
            ArrayList<String> NewHierarchyNames = new ArrayList<String>();
            ArrayList<Netlist> NewHierarchyNetlists = new ArrayList<Netlist>();
            NewHierarchyNames.addAll(HierarchyNames);
            NewHierarchyNames.remove(NewHierarchyNames.size() - 1);
            NewHierarchyNetlists.addAll(HierarchyNetlists);
            NewHierarchyNetlists.remove(NewHierarchyNetlists.size() - 1);
            Netlist SubNetList = HierarchyNetlists.get(HierarchyNetlists.size() - 2);
            Net NewNet = SubNet.GetParrentNet();
            Byte NewNetIndex = SubNet.GetParrentNetBitIndex();
            Set<Wire> Segments = new HashSet<Wire>();
            SourceInfo source = SubNetList.GetHiddenSource(NewNet, NewNetIndex, SubNetList.MyComplexSplitters, null, new HashSet<String>(), Segments, Reporter);
            if (source == null) {
                Reporter.AddFatalError("BUG: Unable to find source in sub-circuit!\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
                return;
            }
            ComponentFactory sfac = source.getSource().GetComp().getFactory();
            if (sfac instanceof Pin || sfac instanceof SubcircuitFactory) {
                SimpleDRCContainer warn = new SimpleDRCContainer(SubNetList.getCircuit(), Strings.get("NetList_GatedClockInt"), SimpleDRCContainer.LEVEL_NORMAL, SimpleDRCContainer.MARK_WIRE, true);
                warn.AddMarkComponents(Segments);
                Reporter.AddWarning(warn);
                SubNetList.WarningTraceForGatedClock(source.getSource(), source.getIndex(), NewHierarchyNetlists, NewHierarchyNames, Reporter);
            } else {
                SimpleDRCContainer warn = new SimpleDRCContainer(SubNetList.getCircuit(), Strings.get("NetList_GatedClockSource"), SimpleDRCContainer.LEVEL_NORMAL, SimpleDRCContainer.MARK_WIRE, true);
                warn.AddMarkComponents(Segments);
                Reporter.AddWarning(warn);
            }
        }
    }
    if (comp.getFactory() instanceof SubcircuitFactory) {
        /* TODO */
        SubcircuitFactory sub = (SubcircuitFactory) comp.getFactory();
        if (Source.getChildsPortIndex() < 0) {
            Reporter.AddFatalError("BUG: Subcircuit port is not annotated!\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
            return;
        }
        NetlistComponent OutputPort = sub.getSubcircuit().getNetList().GetOutputPin(Source.getChildsPortIndex());
        if (OutputPort == null) {
            Reporter.AddFatalError("BUG: Unable to find Subcircuit output port!\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
            return;
        }
        Net ConnectedNet = Source.GetParrentNet();
        /* Find the correct subcircuit */
        NetlistComponent SubCirc = null;
        for (NetlistComponent subc : MySubCircuits) {
            if (subc.GetComponent().equals(Source.GetComp()))
                SubCirc = subc;
        }
        if (SubCirc == null) {
            Reporter.AddFatalError("BUG: Unable to find Subcircuit!\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
            return;
        }
        byte BitIndex = SubCirc.GetConnectionBitIndex(ConnectedNet, (byte) index);
        if (BitIndex < 0) {
            Reporter.AddFatalError("BUG: Unable to find the bit index of a Subcircuit output port!\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
            return;
        }
        ConnectionPoint SubNet = OutputPort.getEnd(0).GetConnection(BitIndex);
        if (SubNet.GetParrentNet() != null) {
            /* we have a connected pin */
            Netlist SubNetList = sub.getSubcircuit().getNetList();
            ArrayList<String> NewHierarchyNames = new ArrayList<String>();
            ArrayList<Netlist> NewHierarchyNetlists = new ArrayList<Netlist>();
            NewHierarchyNames.addAll(HierarchyNames);
            NewHierarchyNames.add(CorrectLabel.getCorrectLabel(SubCirc.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)));
            NewHierarchyNetlists.addAll(HierarchyNetlists);
            NewHierarchyNetlists.add(SubNetList);
            Net NewNet = SubNet.GetParrentNet();
            Byte NewNetIndex = SubNet.GetParrentNetBitIndex();
            Set<Wire> Segments = new HashSet<Wire>();
            SourceInfo source = SubNetList.GetHiddenSource(NewNet, NewNetIndex, SubNetList.MyComplexSplitters, null, new HashSet<String>(), Segments, Reporter);
            if (source == null) {
                Reporter.AddFatalError("BUG: Unable to find source in sub-circuit!\n ==> " + this.getClass().getName().replaceAll("\\.", "/") + ":" + Thread.currentThread().getStackTrace()[2].getLineNumber() + "\n");
                return;
            }
            ComponentFactory sfac = source.getSource().GetComp().getFactory();
            if (sfac instanceof Pin || sfac instanceof SubcircuitFactory) {
                SimpleDRCContainer warn = new SimpleDRCContainer(SubNetList.getCircuit(), Strings.get("NetList_GatedClockInt"), SimpleDRCContainer.LEVEL_NORMAL, SimpleDRCContainer.MARK_WIRE, true);
                warn.AddMarkComponents(Segments);
                Reporter.AddWarning(warn);
                SubNetList.WarningTraceForGatedClock(source.getSource(), source.getIndex(), NewHierarchyNetlists, NewHierarchyNames, Reporter);
            } else {
                SimpleDRCContainer warn = new SimpleDRCContainer(SubNetList.getCircuit(), Strings.get("NetList_GatedClockSource"), SimpleDRCContainer.LEVEL_NORMAL, SimpleDRCContainer.MARK_WIRE, true);
                warn.AddMarkComponents(Segments);
                Reporter.AddWarning(warn);
            }
        }
    }
}

Example 74 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class Netlist method DesignRuleCheckResult.

public int DesignRuleCheckResult(FPGAReport Reporter, String HDLIdentifier, boolean IsTopLevel, ArrayList<String> Sheetnames) {
    ArrayList<String> CompName = new ArrayList<String>();
    Map<String, Component> Labels = new HashMap<String, Component>();
    ArrayList<SimpleDRCContainer> drc = new ArrayList<SimpleDRCContainer>();
    int CommonDRCStatus = DRC_PASSED;
    /* First we go down the tree and get the DRC status of all sub-circuits */
    for (Circuit circ : MySubCircuitMap.keySet()) {
        CommonDRCStatus |= circ.getNetList().DesignRuleCheckResult(Reporter, HDLIdentifier, false, Sheetnames);
    }
    /* Check if we are okay */
    if (DRCStatus == DRC_PASSED) {
        return CommonDRCStatus;
    } else {
        /* There are changes, so we clean up the old information */
        clear();
        DRCStatus = DRC_PASSED;
    /*
									 * we mark already passed, if an error
									 * occurs the status is changed
									 */
    }
    /*
		 * Check for duplicated sheet names, this is bad as we will have
		 * multiple "different" components with the same name
		 */
    if (MyCircuit.getName().isEmpty()) {
        /*
			 * in the current implementation of logisim this should never
			 * happen, but we leave it in
			 */
        Reporter.AddFatalError("Found a sheet in your design with an empty name. This is not allowed, please specify a name!");
        DRCStatus |= DRC_ERROR;
    }
    if (Sheetnames.contains(MyCircuit.getName())) {
        /*
			 * in the current implementation of logisim this should never
			 * happen, but we leave it in
			 */
        Reporter.AddFatalError("Found more than one sheet in your design with the name :\"" + MyCircuit.getName() + "\". This is not allowed, please make sure that all sheets have a unique name!");
        DRCStatus |= DRC_ERROR;
    } else {
        Sheetnames.add(MyCircuit.getName());
    }
    /* Preparing stage */
    for (Component comp : MyCircuit.getNonWires()) {
        String ComponentName = comp.getFactory().getHDLName(comp.getAttributeSet());
        if (!CompName.contains(ComponentName)) {
            CompName.add(ComponentName);
        }
    }
    drc.clear();
    drc.add(new SimpleDRCContainer(MyCircuit, Strings.get("HDL_noLabel"), SimpleDRCContainer.LEVEL_FATAL, SimpleDRCContainer.MARK_INSTANCE));
    drc.add(new SimpleDRCContainer(MyCircuit, Strings.get("HDL_CompNameIsLabel"), SimpleDRCContainer.LEVEL_FATAL, SimpleDRCContainer.MARK_INSTANCE | SimpleDRCContainer.MARK_LABEL));
    drc.add(new SimpleDRCContainer(MyCircuit, Strings.get("HDL_LabelInvalid"), SimpleDRCContainer.LEVEL_FATAL, SimpleDRCContainer.MARK_INSTANCE | SimpleDRCContainer.MARK_LABEL));
    drc.add(new SimpleDRCContainer(MyCircuit, Strings.get("HDL_DuplicatedLabels"), SimpleDRCContainer.LEVEL_FATAL, SimpleDRCContainer.MARK_INSTANCE | SimpleDRCContainer.MARK_LABEL));
    drc.add(new SimpleDRCContainer(MyCircuit, Strings.get("HDL_Tristate"), SimpleDRCContainer.LEVEL_FATAL, SimpleDRCContainer.MARK_INSTANCE));
    drc.add(new SimpleDRCContainer(MyCircuit, Strings.get("HDL_unsupported"), SimpleDRCContainer.LEVEL_FATAL, SimpleDRCContainer.MARK_INSTANCE));
    for (Component comp : MyCircuit.getNonWires()) {
        /*
			 * Here we check if the components are supported for the HDL
			 * generation
			 */
        if (!comp.getFactory().HDLSupportedComponent(HDLIdentifier, comp.getAttributeSet())) {
            drc.get(5).AddMarkComponent(comp);
            DRCStatus |= DRC_ERROR;
        }
        /*
			 * we check that all components that require a non zero label
			 * (annotation) have a label set
			 */
        if (comp.getFactory().RequiresNonZeroLabel()) {
            String Label = CorrectLabel.getCorrectLabel(comp.getAttributeSet().getValue(StdAttr.LABEL).toString()).toUpperCase();
            String ComponentName = comp.getFactory().getHDLName(comp.getAttributeSet());
            if (Label.isEmpty()) {
                drc.get(0).AddMarkComponent(comp);
                DRCStatus |= ANNOTATE_REQUIRED;
            } else {
                if (CompName.contains(Label)) {
                    drc.get(1).AddMarkComponent(comp);
                    DRCStatus |= DRC_ERROR;
                }
                if (!CorrectLabel.IsCorrectLabel(Label, HDLIdentifier)) {
                    /* this should not happen anymore */
                    drc.get(2).AddMarkComponent(comp);
                    DRCStatus |= DRC_ERROR;
                }
                if (Labels.containsKey(Label)) {
                    drc.get(3).AddMarkComponent(comp);
                    drc.get(3).AddMarkComponent(Labels.get(Label));
                    DRCStatus |= DRC_ERROR;
                } else {
                    Labels.put(Label, comp);
                }
            }
            if (comp.getFactory() instanceof SubcircuitFactory) {
                /* Special care has to be taken for sub-circuits */
                if (Label.equals(ComponentName.toUpperCase())) {
                    drc.get(1).AddMarkComponent(comp);
                    DRCStatus |= DRC_ERROR;
                }
                if (!CorrectLabel.IsCorrectLabel(comp.getFactory().getName(), HDLIdentifier, "Found that the component \"" + comp.getFactory().getName() + "\" in circuit \"" + MyCircuit.getName(), Reporter)) {
                    DRCStatus |= DRC_ERROR;
                }
                SubcircuitFactory sub = (SubcircuitFactory) comp.getFactory();
                LocalNrOfInportBubles = LocalNrOfInportBubles + sub.getSubcircuit().getNetList().NumberOfInputBubbles();
                LocalNrOfOutportBubles = LocalNrOfOutportBubles + sub.getSubcircuit().getNetList().NumberOfOutputBubbles();
                LocalNrOfInOutBubles = LocalNrOfInOutBubles + sub.getSubcircuit().getNetList().NumberOfInOutBubbles();
            }
        }
        /* Now we check that no tri-state are present */
        if (comp.getFactory().HasThreeStateDrivers(comp.getAttributeSet())) {
            drc.get(4).AddMarkComponent(comp);
            DRCStatus |= DRC_ERROR;
        }
    }
    for (int i = 0; i < drc.size(); i++) if (drc.get(i).DRCInfoPresent())
        Reporter.AddError(drc.get(i));
    drc.clear();
    /* Here we have to quit as the netlist generation needs a clean tree */
    if ((DRCStatus | CommonDRCStatus) != DRC_PASSED) {
        return DRCStatus | CommonDRCStatus;
    }
    /*
		 * Okay we now know for sure that all elements are supported, lets build
		 * the net list
		 */
    Reporter.AddInfo("Building netlist for sheet \"" + MyCircuit.getName() + "\"");
    if (!this.GenerateNetlist(Reporter, HDLIdentifier)) {
        this.clear();
        DRCStatus = DRC_ERROR;
        /*
			 * here we have to quit, as all the following steps depend on a
			 * proper netlist
			 */
        return DRCStatus | CommonDRCStatus;
    }
    if (NetlistHasShortCircuits(Reporter)) {
        clear();
        DRCStatus = DRC_ERROR;
        return DRCStatus | CommonDRCStatus;
    }
    /* Check for connections without a source */
    NetlistHasSinksWithoutSource(Reporter);
    /* Check for unconnected input pins on components and generate warnings */
    for (NetlistComponent comp : MyComponents) {
        boolean openInputs = false;
        for (int j = 0; j < comp.NrOfEnds(); j++) {
            if (comp.EndIsInput(j) && !comp.EndIsConnected(j))
                openInputs = true;
        }
        if (openInputs) {
            SimpleDRCContainer warn = new SimpleDRCContainer(MyCircuit, Strings.get("NetList_UnconnectedInputs"), SimpleDRCContainer.LEVEL_NORMAL, SimpleDRCContainer.MARK_INSTANCE);
            warn.AddMarkComponent(comp.GetComponent());
            Reporter.AddWarning(warn);
        }
    }
    /* Check for unconnected input pins on subcircuits and generate warnings */
    for (NetlistComponent comp : MySubCircuits) {
        boolean openInputs = false;
        for (int j = 0; j < comp.NrOfEnds(); j++) {
            if (comp.EndIsInput(j) && !comp.EndIsConnected(j))
                openInputs = true;
        }
        if (openInputs) {
            SimpleDRCContainer warn = new SimpleDRCContainer(MyCircuit, Strings.get("NetList_UnconnectedInputs"), SimpleDRCContainer.LEVEL_SEVERE, SimpleDRCContainer.MARK_INSTANCE);
            warn.AddMarkComponent(comp.GetComponent());
            Reporter.AddWarning(warn);
        }
    }
    /* Only if we are on the top-level we are going to build the clock-tree */
    if (IsTopLevel) {
        if (!DetectClockTree(Reporter)) {
            DRCStatus = DRC_ERROR;
            return DRCStatus | CommonDRCStatus;
        }
        ConstructHierarchyTree(null, new ArrayList<String>(), new Integer(0), new Integer(0), new Integer(0));
        int ports = NumberOfInputPorts() + NumberOfOutputPorts() + LocalNrOfInportBubles + LocalNrOfOutportBubles + LocalNrOfInOutBubles;
        if (ports == 0) {
            Reporter.AddFatalError("Toplevel \"" + MyCircuit.getName() + "\" has no input(s) and/or no output(s)!");
            DRCStatus = DRC_ERROR;
            return DRCStatus | CommonDRCStatus;
        }
        /* Check for gated clocks */
        if (!DetectGatedClocks(Reporter)) {
            DRCStatus = DRC_ERROR;
            return DRCStatus | CommonDRCStatus;
        }
    }
    Reporter.AddInfo("Circuit \"" + MyCircuit.getName() + "\" has " + NumberOfNets() + " nets and " + NumberOfBusses() + " busses.");
    Reporter.AddInfo("Circuit \"" + MyCircuit.getName() + "\" passed DRC check");
    DRCStatus = DRC_PASSED;
    return DRCStatus | CommonDRCStatus;
}

Example 75 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class Netlist method GetHiddenSinks.

private ArrayList<ConnectionPoint> GetHiddenSinks(Net thisNet, Byte bitIndex, ArrayList<Component> SplitterList, Component ActiveSplitter, Set<String> HandledNets, Boolean isSourceNet) {
    ArrayList<ConnectionPoint> result = new ArrayList<ConnectionPoint>();
    /*
		 * to prevent deadlock situations we check if we already looked at this
		 * net
		 */
    String NetId = Integer.toString(MyNets.indexOf(thisNet)) + "-" + Byte.toString(bitIndex);
    if (HandledNets.contains(NetId)) {
        return result;
    } else {
        HandledNets.add(NetId);
    }
    if (thisNet.hasBitSinks(bitIndex) && !isSourceNet) {
        result.addAll(thisNet.GetBitSinks(bitIndex));
    }
    /* Check if we have a connection to another splitter */
    for (Component currentSplitter : SplitterList) {
        if (ActiveSplitter != null) {
            if (currentSplitter.equals(ActiveSplitter)) {
                continue;
            }
        }
        List<EndData> ends = currentSplitter.getEnds();
        for (byte end = 0; end < ends.size(); end++) {
            if (thisNet.contains(ends.get(end).getLocation())) {
                /* Here we have to process the inherited bits of the parent */
                byte[] BusBitConnection = ((Splitter) currentSplitter).GetEndpoints();
                if (end == 0) {
                    /* this is a main net, find the connected end */
                    Byte SplitterEnd = BusBitConnection[bitIndex];
                    /* Find the corresponding Net index */
                    Byte Netindex = 0;
                    for (int index = 0; index < bitIndex; index++) {
                        if (BusBitConnection[index] == SplitterEnd) {
                            Netindex++;
                        }
                    }
                    /* Find the connected Net */
                    Net SlaveNet = null;
                    for (Net thisnet : MyNets) {
                        if (thisnet.contains(ends.get(SplitterEnd).getLocation())) {
                            SlaveNet = thisnet;
                        }
                    }
                    if (SlaveNet != null) {
                        if (SlaveNet.IsRootNet()) {
                            /* Trace down the slavenet */
                            result.addAll(GetHiddenSinks(SlaveNet, Netindex, SplitterList, currentSplitter, HandledNets, false));
                        } else {
                            result.addAll(GetHiddenSinks(SlaveNet.getParent(), SlaveNet.getBit(Netindex), SplitterList, currentSplitter, HandledNets, false));
                        }
                    }
                } else {
                    ArrayList<Byte> Rootindices = new ArrayList<Byte>();
                    for (byte b = 0; b < BusBitConnection.length; b++) {
                        if (BusBitConnection[b] == end) {
                            Rootindices.add(b);
                        }
                    }
                    Net RootNet = null;
                    for (Net thisnet : MyNets) {
                        if (thisnet.contains(currentSplitter.getEnd(0).getLocation())) {
                            RootNet = thisnet;
                        }
                    }
                    if (RootNet != null) {
                        if (RootNet.IsRootNet()) {
                            result.addAll(GetHiddenSinks(RootNet, Rootindices.get(bitIndex), SplitterList, currentSplitter, HandledNets, false));
                        } else {
                            result.addAll(GetHiddenSinks(RootNet.getParent(), RootNet.getBit(Rootindices.get(bitIndex)), SplitterList, currentSplitter, HandledNets, false));
                        }
                    }
                }
            }
        }
    }
    return result;
}