Examples with Component com.cburch.logisim.comp.Component used on opensource projects

Example 41 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class ReptarLocalBusHDLGeneratorFactory method GetInlinedCode.

@Override
public ArrayList<String> GetInlinedCode(String HDLType, ArrayList<String> ComponentIdentifier, FPGAReport Reporter, MappableResourcesContainer MapInfo) {
    ArrayList<String> Contents = new ArrayList<String>();
    StringBuffer Temp = new StringBuffer();
    int OutputId = MapInfo.GetFPGAOutputPinId(MapInfo.GetMapNamesList(ComponentIdentifier).get(0));
    Component ThisPin = MapInfo.GetComponent(ComponentIdentifier).GetComponent();
    Temp.append("   ");
    Temp.append(HDLGeneratorFactory.FPGAOutputPinName);
    Temp.append("_" + Integer.toString(OutputId));
    Temp.append(" <= ");
    Temp.append(" NOT ");
    Temp.append("s_" + CorrectLabel.getCorrectLabel(ThisPin.getAttributeSet().getValue(StdAttr.LABEL)));
    Temp.append(";");
    Contents.add(Temp.toString());
    // Contents.add("YOUHOU");
    return Contents;
}

Example 42 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class VhdlSimulatorVhdlTop method generate.

public void generate() {
    /* Do not generate if file is already valid */
    if (valid)
        return;
    String[] type = { "inout", "in", "out" };
    StringBuilder ports = new StringBuilder();
    ports.append("Autogenerated by logisim --");
    ports.append(System.getProperty("line.separator"));
    StringBuilder components = new StringBuilder();
    components.append("Autogenerated by logisim --");
    components.append(System.getProperty("line.separator"));
    StringBuilder map = new StringBuilder();
    map.append("Autogenerated by logisim --");
    map.append(System.getProperty("line.separator"));
    Boolean firstPort = true, firstComp = true, firstMap = true;
    /* For each vhdl entity */
    for (Component comp : VhdlSimulator.getVhdlComponents(vhdlSimulator.getProject().getCircuitState())) {
        if (comp.getFactory().getClass().equals(VhdlEntity.class)) {
            InstanceState state = vhdlSimulator.getProject().getCircuitState().getInstanceState(comp);
            VhdlContent content = state.getAttributeValue(VhdlEntity.CONTENT_ATTR);
            String vhdlEntityName = comp.getFactory().getHDLTopName(state.getInstance().getAttributeSet());
            /*
				 * Create ports
				 */
            for (Port port : content.getPorts()) {
                if (!firstPort) {
                    ports.append(";");
                    ports.append(System.getProperty("line.separator"));
                } else {
                    firstPort = false;
                }
                String portName = vhdlEntityName + "_" + port.getToolTip();
                ports.append("		" + portName + " : " + type[port.getType()] + " std_logic");
                int width = port.getFixedBitWidth().getWidth();
                if (width > 1) {
                    ports.append("_vector(" + (width - 1) + " downto 0)");
                }
            }
            /*
				 * Create components
				 */
            components.append("	component " + vhdlEntityName);
            components.append(System.getProperty("line.separator"));
            components.append("		port (");
            components.append(System.getProperty("line.separator"));
            firstComp = true;
            for (Port port : content.getPorts()) {
                if (!firstComp) {
                    components.append(";");
                    components.append(System.getProperty("line.separator"));
                } else
                    firstComp = false;
                components.append("			" + port.getToolTip() + " : " + type[port.getType()] + " std_logic");
                int width = port.getFixedBitWidth().getWidth();
                if (width > 1) {
                    components.append("_vector(" + (width - 1) + " downto 0)");
                }
            }
            components.append(System.getProperty("line.separator"));
            components.append("		);");
            components.append(System.getProperty("line.separator"));
            components.append("	end component ;");
            components.append(System.getProperty("line.separator"));
            components.append("	");
            components.append(System.getProperty("line.separator"));
            /*
				 * Create port map
				 */
            map.append("	" + vhdlEntityName + "_map : " + vhdlEntityName + " port map (");
            map.append(System.getProperty("line.separator"));
            firstMap = true;
            for (Port port : content.getPorts()) {
                if (!firstMap) {
                    map.append(",");
                    map.append(System.getProperty("line.separator"));
                } else
                    firstMap = false;
                map.append("		" + port.getToolTip() + " => " + vhdlEntityName + "_" + port.getToolTip());
            }
            map.append(System.getProperty("line.separator"));
            map.append("	);");
            map.append(System.getProperty("line.separator"));
            map.append("	");
            map.append(System.getProperty("line.separator"));
        }
    }
    ports.append(System.getProperty("line.separator"));
    ports.append("		---------------------------");
    ports.append(System.getProperty("line.separator"));
    components.append("	---------------------------");
    components.append(System.getProperty("line.separator"));
    map.append("	---------------------------");
    map.append(System.getProperty("line.separator"));
    /*
		 * Replace template blocks by generated datas
		 */
    String template;
    try {
        template = new String(FileUtil.getBytes(this.getClass().getResourceAsStream(VhdlSimulator.VHDL_TEMPLATES_PATH + "top_sim.templ")));
    } catch (IOException e) {
        logger.error("Could not read template : {}", e.getMessage());
        return;
    }
    template = template.replaceAll("%date%", LocaleManager.parserSDF.format(new Date()));
    template = template.replaceAll("%ports%", ports.toString());
    template = template.replaceAll("%components%", components.toString());
    template = template.replaceAll("%map%", map.toString());
    PrintWriter writer;
    try {
        writer = new PrintWriter(VhdlSimulator.SIM_SRC_PATH + VhdlSimulator.SIM_TOP_FILENAME, "UTF-8");
        writer.print(template);
        writer.close();
    } catch (FileNotFoundException e) {
        logger.error("Could not create top_sim file : {}", e.getMessage());
        e.printStackTrace();
        return;
    } catch (UnsupportedEncodingException e) {
        logger.error("Could not create top_sim file : {}", e.getMessage());
        e.printStackTrace();
        return;
    }
    valid = true;
}

Example 43 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class TtyInterface method loadRam.

private static boolean loadRam(CircuitState circState, File loadFile) throws IOException {
    if (loadFile == null)
        return false;
    boolean found = false;
    for (Component comp : circState.getCircuit().getNonWires()) {
        if (comp.getFactory() instanceof Ram) {
            Ram ramFactory = (Ram) comp.getFactory();
            InstanceState ramState = circState.getInstanceState(comp);
            ramFactory.loadImage(ramState, loadFile);
            found = true;
        }
    }
    for (CircuitState sub : circState.getSubstates()) {
        found |= loadRam(sub, loadFile);
    }
    return found;
}

Example 44 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class TtyInterface method prepareForTty.

private static boolean prepareForTty(CircuitState circState, ArrayList<InstanceState> keybStates) {
    boolean found = false;
    for (Component comp : circState.getCircuit().getNonWires()) {
        Object factory = comp.getFactory();
        if (factory instanceof Tty) {
            Tty ttyFactory = (Tty) factory;
            InstanceState ttyState = circState.getInstanceState(comp);
            ttyFactory.sendToStdout(ttyState);
            found = true;
        } else if (factory instanceof Keyboard) {
            keybStates.add(circState.getInstanceState(comp));
            found = true;
        }
    }
    for (CircuitState sub : circState.getSubstates()) {
        found |= prepareForTty(sub, keybStates);
    }
    return found;
}

Example 45 with Component

use of com.cburch.logisim.comp.Component in project logisim-evolution by reds-heig.

the class SimulationTreeCircuitNode method computeChildren.

// returns true if changed
private boolean computeChildren() {
    ArrayList<TreeNode> newChildren = new ArrayList<TreeNode>();
    ArrayList<Component> subcircs = new ArrayList<Component>();
    for (Component comp : circuitState.getCircuit().getNonWires()) {
        if (comp.getFactory() instanceof SubcircuitFactory) {
            subcircs.add(comp);
        } else {
            TreeNode toAdd = model.mapComponentToNode(comp);
            if (toAdd != null) {
                newChildren.add(toAdd);
            }
        }
    }
    Collections.sort(newChildren, new CompareByName());
    Collections.sort(subcircs, this);
    for (Component comp : subcircs) {
        SubcircuitFactory factory = (SubcircuitFactory) comp.getFactory();
        CircuitState state = factory.getSubstate(circuitState, comp);
        SimulationTreeCircuitNode toAdd = null;
        for (TreeNode o : children) {
            if (o instanceof SimulationTreeCircuitNode) {
                SimulationTreeCircuitNode n = (SimulationTreeCircuitNode) o;
                if (n.circuitState == state) {
                    toAdd = n;
                    break;
                }
            }
        }
        if (toAdd == null) {
            toAdd = new SimulationTreeCircuitNode(model, this, state, comp);
        }
        newChildren.add(toAdd);
    }
    if (!children.equals(newChildren)) {
        children = newChildren;
        return true;
    } else {
        return false;
    }
}