Examples with Circuit com.cburch.logisim.circuit.Circuit used on opensource projects

Example 56 with Circuit

use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.

the class AddTool method mouseReleased.

@Override
public void mouseReleased(Canvas canvas, Graphics g, MouseEvent e) {
    Component added = null;
    if (state == SHOW_ADD) {
        Circuit circ = canvas.getCircuit();
        if (!canvas.getProject().getLogisimFile().contains(circ))
            return;
        if (shouldSnap)
            Canvas.snapToGrid(e);
        moveTo(canvas, g, e.getX(), e.getY());
        Location loc = Location.create(e.getX(), e.getY());
        ComponentFactory source = getFactory();
        AttributeSet attrsCopy = (AttributeSet) attrs.clone();
        if (attrsCopy.containsAttribute(StdAttr.LABEL)) {
            attrsCopy.setValue(StdAttr.LABEL, AutoLabler.GetCurrent(canvas.getCircuit(), source));
            if (AutoLabler.IsActive(canvas.getCircuit())) {
                if (AutoLabler.hasNext(canvas.getCircuit()))
                    AutoLabler.GetNext(canvas.getCircuit(), source);
                else
                    AutoLabler.Stop(canvas.getCircuit());
            } else
                AutoLabler.SetLabel("", canvas.getCircuit(), source);
        }
        if (source == null)
            return;
        Component c = source.createComponent(loc, attrsCopy);
        if (circ.hasConflict(c)) {
            canvas.setErrorMessage(Strings.getter("exclusiveError"));
            return;
        }
        Bounds bds = c.getBounds(g);
        if (bds.getX() < 0 || bds.getY() < 0) {
            canvas.setErrorMessage(Strings.getter("negativeCoordError"));
            return;
        }
        try {
            CircuitMutation mutation = new CircuitMutation(circ);
            mutation.add(c);
            Action action = mutation.toAction(Strings.getter("addComponentAction", factory.getDisplayGetter()));
            canvas.getProject().doAction(action);
            lastAddition = action;
            added = c;
            canvas.repaint();
        } catch (CircuitException ex) {
            JOptionPane.showMessageDialog(canvas.getProject().getFrame(), ex.getMessage());
        }
        setState(canvas, SHOW_GHOST);
    } else if (state == SHOW_ADD_NO) {
        setState(canvas, SHOW_NONE);
    }
    Project proj = canvas.getProject();
    Tool next = determineNext(proj);
    if (next != null) {
        proj.setTool(next);
        Action act = SelectionActions.dropAll(canvas.getSelection());
        if (act != null) {
            proj.doAction(act);
        }
        if (added != null)
            canvas.getSelection().add(added);
    }
}

Example 57 with Circuit

use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.

the class EditTool method isWiringPoint.

private boolean isWiringPoint(Canvas canvas, Location loc, int modsEx) {
    boolean wiring = (modsEx & MouseEvent.ALT_DOWN_MASK) == 0;
    boolean select = !wiring;
    if (canvas != null && canvas.getSelection() != null) {
        Collection<Component> sel = canvas.getSelection().getComponents();
        if (sel != null) {
            for (Component c : sel) {
                if (c instanceof Wire) {
                    Wire w = (Wire) c;
                    if (w.contains(loc) && !w.endsAt(loc))
                        return select;
                }
            }
        }
    }
    Circuit circ = canvas.getCircuit();
    Collection<? extends Component> at = circ.getComponents(loc);
    if (at != null && at.size() > 0)
        return wiring;
    for (Wire w : circ.getWires()) {
        if (w.contains(loc)) {
            return wiring;
        }
    }
    return select;
}

Example 58 with Circuit

use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.

the class FPGACommanderGui method writeHDL.

private boolean writeHDL() {
    String CircuitName = circuitsList.getSelectedItem().toString();
    if (!GenDirectory(AppPreferences.FPGA_Workspace.get() + File.separator + MyProject.getLogisimFile().getName())) {
        MyReporter.AddFatalError("Unable to create directory: \"" + AppPreferences.FPGA_Workspace.get() + File.separator + MyProject.getLogisimFile().getName() + "\"");
        return false;
    }
    String ProjectDir = AppPreferences.FPGA_Workspace.get() + File.separator + MyProject.getLogisimFile().getName();
    if (!ProjectDir.endsWith(File.separator)) {
        ProjectDir += File.separator;
    }
    LogisimFile myfile = MyProject.getLogisimFile();
    Circuit RootSheet = myfile.getCircuit(CircuitName);
    ProjectDir += CorrectLabel.getCorrectLabel(RootSheet.getName()) + File.separator;
    if (!CleanDirectory(ProjectDir)) {
        MyReporter.AddFatalError("Unable to cleanup old project files in directory: \"" + ProjectDir + "\"");
        return false;
    }
    if (!GenDirectory(ProjectDir)) {
        MyReporter.AddFatalError("Unable to create directory: \"" + ProjectDir + "\"");
        return false;
    }
    for (int i = 0; i < HDLPaths.length; i++) {
        if (!GenDirectory(ProjectDir + HDLPaths[i])) {
            MyReporter.AddFatalError("Unable to create directory: \"" + ProjectDir + HDLPaths[i] + "\"");
            return false;
        }
    }
    Set<String> GeneratedHDLComponents = new HashSet<String>();
    HDLGeneratorFactory Worker = RootSheet.getSubcircuitFactory().getHDLGenerator(AppPreferences.HDL_Type.get(), RootSheet.getStaticAttributes());
    if (Worker == null) {
        MyReporter.AddFatalError("Internal error on HDL generation, null pointer exception");
        return false;
    }
    if (!Worker.GenerateAllHDLDescriptions(GeneratedHDLComponents, ProjectDir, null, MyReporter, AppPreferences.HDL_Type.get())) {
        return false;
    }
    /* Here we generate the top-level shell */
    if (RootSheet.getNetList().NumberOfClockTrees() > 0) {
        TickComponentHDLGeneratorFactory Ticker = new TickComponentHDLGeneratorFactory(MyBoardInformation.fpga.getClockFrequency(), MenuSimulate.SupportedTickFrequencies[frequenciesList.getSelectedIndex()]);
        if (!AbstractHDLGeneratorFactory.WriteEntity(ProjectDir + Ticker.GetRelativeDirectory(AppPreferences.HDL_Type.get()), Ticker.GetEntity(RootSheet.getNetList(), null, Ticker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get()), Ticker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get())) {
            return false;
        }
        if (!AbstractHDLGeneratorFactory.WriteArchitecture(ProjectDir + Ticker.GetRelativeDirectory(AppPreferences.HDL_Type.get()), Ticker.GetArchitecture(RootSheet.getNetList(), null, Ticker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get()), Ticker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get())) {
            return false;
        }
        HDLGeneratorFactory ClockGen = RootSheet.getNetList().GetAllClockSources().get(0).getFactory().getHDLGenerator(AppPreferences.HDL_Type.get(), RootSheet.getNetList().GetAllClockSources().get(0).getAttributeSet());
        String CompName = RootSheet.getNetList().GetAllClockSources().get(0).getFactory().getHDLName(null);
        if (!AbstractHDLGeneratorFactory.WriteEntity(ProjectDir + ClockGen.GetRelativeDirectory(AppPreferences.HDL_Type.get()), ClockGen.GetEntity(RootSheet.getNetList(), null, CompName, MyReporter, AppPreferences.HDL_Type.get()), CompName, MyReporter, AppPreferences.HDL_Type.get())) {
            return false;
        }
        if (!AbstractHDLGeneratorFactory.WriteArchitecture(ProjectDir + ClockGen.GetRelativeDirectory(AppPreferences.HDL_Type.get()), ClockGen.GetArchitecture(RootSheet.getNetList(), null, CompName, MyReporter, AppPreferences.HDL_Type.get()), CompName, MyReporter, AppPreferences.HDL_Type.get())) {
            return false;
        }
    }
    Worker = new ToplevelHDLGeneratorFactory(MyBoardInformation.fpga.getClockFrequency(), MenuSimulate.SupportedTickFrequencies[frequenciesList.getSelectedIndex()], RootSheet, MyMappableResources);
    if (!AbstractHDLGeneratorFactory.WriteEntity(ProjectDir + Worker.GetRelativeDirectory(AppPreferences.HDL_Type.get()), Worker.GetEntity(RootSheet.getNetList(), null, ToplevelHDLGeneratorFactory.FPGAToplevelName, MyReporter, AppPreferences.HDL_Type.get()), Worker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get())) {
        return false;
    }
    if (!AbstractHDLGeneratorFactory.WriteArchitecture(ProjectDir + Worker.GetRelativeDirectory(AppPreferences.HDL_Type.get()), Worker.GetArchitecture(RootSheet.getNetList(), null, ToplevelHDLGeneratorFactory.FPGAToplevelName, MyReporter, AppPreferences.HDL_Type.get()), Worker.getComponentStringIdentifier(), MyReporter, AppPreferences.HDL_Type.get())) {
        return false;
    }
    return true;
}

Example 59 with Circuit

use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.

the class FPGACommanderGui method MapDesign.

private boolean MapDesign() {
    String CircuitName = circuitsList.getSelectedItem().toString();
    LogisimFile myfile = MyProject.getLogisimFile();
    Circuit RootSheet = myfile.getCircuit(CircuitName);
    Netlist RootNetlist = RootSheet.getNetList();
    if (MyBoardInformation == null) {
        MyReporter.AddError("INTERNAL ERROR: No board information available ?!?");
        return false;
    }
    Map<String, ArrayList<Integer>> BoardComponents = MyBoardInformation.GetComponents();
    MyReporter.AddInfo("The Board " + MyBoardInformation.getBoardName() + " has:");
    for (String key : BoardComponents.keySet()) {
        MyReporter.AddInfo(BoardComponents.get(key).size() + " " + key + "(s)");
    }
    /*
		 * At this point I require 2 sorts of information: 1) A hierarchical
		 * netlist of all the wires that needs to be bubbled up to the toplevel
		 * in order to connect the LEDs, Buttons, etc. (hence for the HDL
		 * generation). 2) A list with all components that are required to be
		 * mapped to PCB components. Identification can be done by a hierarchy
		 * name plus component/sub-circuit name
		 */
    MyMappableResources = new MappableResourcesContainer(MyBoardInformation, RootNetlist);
    if (!MyMappableResources.IsMappable(BoardComponents, MyReporter)) {
        return false;
    }
    MapPannel.SetBoardInformation(MyBoardInformation);
    MapPannel.SetMappebleComponents(MyMappableResources);
    panel.setVisible(false);
    MapPannel.SetVisible(true);
    panel.setVisible(true);
    if (MyMappableResources.UnmappedList().isEmpty()) {
        MyMappableResources.BuildIOMappingInformation();
        return true;
    }
    MyReporter.AddError("Not all IO components have been mapped to the board " + MyBoardInformation.getBoardName() + " please map all components to continue!");
    return false;
}

Example 60 with Circuit

use of com.cburch.logisim.circuit.Circuit in project logisim-evolution by reds-heig.

the class FPGACommanderGui method RebuildCircuitSelection.

private void RebuildCircuitSelection() {
    circuitsList.removeAllItems();
    panel.setTitle("FPGA Commander : " + MyProject.getLogisimFile().getName());
    int i = 0;
    for (Circuit thisone : MyProject.getLogisimFile().getCircuits()) {
        circuitsList.addItem(thisone.getName());
        thisone.removeCircuitListener(this);
        thisone.addCircuitListener(this);
        if (thisone.getName().equals(MyProject.getCurrentCircuit().getName())) {
            circuitsList.setSelectedIndex(i);
        }
        i++;
    }
}