Examples with NetlistComponent com.bfh.logisim.designrulecheck.NetlistComponent used on opensource projects

Example 6 with NetlistComponent

use of com.bfh.logisim.designrulecheck.NetlistComponent in project logisim-evolution by reds-heig.

the class AbstractHDLGeneratorFactory method GetInlinedCode.

public ArrayList<String> GetInlinedCode(String HDLType, ArrayList<String> ComponentIdentifier, FPGAReport Reporter, MappableResourcesContainer MapInfo) {
    ArrayList<String> Contents = new ArrayList<String>();
    String Preamble = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? "" : "assign ";
    String AssignOperator = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? " <= " : " = ";
    String OpenBracket = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? "(" : "[";
    String CloseBracket = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? ")" : "]";
    String Inversion = (HDLType.equals(HDLGeneratorFactory.VHDL)) ? "NOT " : "~";
    StringBuffer Temp = new StringBuffer();
    NetlistComponent comp = MapInfo.GetComponent(ComponentIdentifier);
    if (comp == null) {
        Reporter.AddFatalError("Component not found, bizar");
        return Contents;
    }
    ArrayList<String> bla = new ArrayList<String>();
    bla.addAll(ComponentIdentifier);
    bla.remove(0);
    BubbleInformationContainer BubbleInfo = comp.GetGlobalBubbleId(bla);
    if (BubbleInfo == null) {
        Reporter.AddFatalError("Component has no bubble information, bizar! " + bla.toString());
        return Contents;
    }
    /* The button is simple as it has only 1 pin */
    /*
		 * The bubble information presents the internal pin location, we now
		 * need to know the input pin index
		 */
    ArrayList<String> MyMaps = MapInfo.GetMapNamesList(ComponentIdentifier);
    if (MyMaps == null) {
        Reporter.AddFatalError("Component has no map information, bizar! " + ComponentIdentifier.toString());
        return Contents;
    }
    int BubbleOffset = 0;
    for (int MapOffset = 0; MapOffset < MyMaps.size(); MapOffset++) {
        String map = MyMaps.get(MapOffset);
        int InputId = MapInfo.GetFPGAInputPinId(map);
        int OutputId = MapInfo.GetFPGAOutputPinId(map);
        int NrOfPins = MapInfo.GetNrOfPins(map);
        boolean Invert = MapInfo.RequiresToplevelInversion(ComponentIdentifier, map);
        for (int PinId = 0; PinId < NrOfPins; PinId++) {
            Temp.setLength(0);
            Temp.append("   " + Preamble);
            if (InputId >= 0 && ((BubbleInfo.GetInputStartIndex() + BubbleOffset) <= BubbleInfo.GetInputEndIndex())) {
                Temp.append("s_" + HDLGeneratorFactory.LocalInputBubbleBusname + OpenBracket);
                Temp.append(BubbleInfo.GetInputStartIndex() + BubbleOffset);
                BubbleOffset++;
                Temp.append(CloseBracket + AssignOperator);
                if (Invert) {
                    Temp.append(Inversion);
                }
                Temp.append(HDLGeneratorFactory.FPGAInputPinName);
                Temp.append("_" + Integer.toString(InputId + PinId) + ";");
                Contents.add(Temp.toString());
            }
            Temp.setLength(0);
            Temp.append("   " + Preamble);
            if (OutputId >= 0 && ((BubbleInfo.GetOutputStartIndex() + BubbleOffset) <= BubbleInfo.GetOutputEndIndex())) {
                Temp.append(HDLGeneratorFactory.FPGAOutputPinName);
                Temp.append("_" + Integer.toString(OutputId + PinId) + AssignOperator);
                if (Invert) {
                    Temp.append(Inversion);
                }
                Temp.append("s_" + HDLGeneratorFactory.LocalOutputBubbleBusname + OpenBracket);
                Temp.append(BubbleInfo.GetOutputStartIndex() + BubbleOffset);
                BubbleOffset++;
                Temp.append(CloseBracket + ";");
                Contents.add(Temp.toString());
            }
        }
    }
    return Contents;
}

Example 7 with NetlistComponent

use of com.bfh.logisim.designrulecheck.NetlistComponent in project logisim-evolution by reds-heig.

the class CircuitHDLGeneratorFactory method GetModuleFunctionality.

@Override
public ArrayList<String> GetModuleFunctionality(Netlist TheNetlist, AttributeSet attrs, FPGAReport Reporter, String HDLType) {
    ArrayList<String> Contents = new ArrayList<String>();
    String Preamble = (HDLType.equals(VHDL)) ? "" : "assign ";
    String AssignmentOperator = (HDLType.equals(VHDL)) ? "<= " : "= ";
    String OpenBracket = (HDLType.equals(VHDL)) ? "(" : "[";
    String CloseBracket = (HDLType.equals(VHDL)) ? ")" : "]";
    boolean FirstLine = true;
    StringBuffer Temp = new StringBuffer();
    Map<String, Long> CompIds = new HashMap<String, Long>();
    /* we start with the connection of the clock sources */
    for (NetlistComponent ClockSource : TheNetlist.GetClockSources()) {
        if (FirstLine) {
            Contents.add("");
            Contents.addAll(MakeRemarkBlock("Here all clock generator connections are defined", 3, HDLType));
            FirstLine = false;
        }
        if (!ClockSource.EndIsConnected(0)) {
            if (ClockSource.GetComponent().getAttributeSet().getValue(StdAttr.LABEL).equals("sysclk")) {
                Reporter.AddInfo("Clock component found with no connection, skipping: '" + ClockSource.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "'");
            } else {
                Reporter.AddWarning("Clock component found with no connection, skipping: '" + ClockSource.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "'");
            }
            continue;
        }
        String ClockNet = GetClockNetName(ClockSource, 0, TheNetlist);
        if (ClockNet.isEmpty()) {
            Reporter.AddFatalError("INTERNAL ERROR: Cannot find clocknet!");
        }
        String ConnectedNet = GetNetName(ClockSource, 0, true, HDLType, TheNetlist);
        Temp.setLength(0);
        Temp.append(ConnectedNet);
        while (Temp.length() < SallignmentSize) {
            Temp.append(" ");
        }
        if (!TheNetlist.RequiresGlobalClockConnection()) {
            Contents.add("   " + Preamble + Temp.toString() + AssignmentOperator + ClockNet + OpenBracket + Integer.toString(ClockHDLGeneratorFactory.DerivedClockIndex) + CloseBracket + ";");
        } else {
            Contents.add("   " + Preamble + Temp.toString() + AssignmentOperator + TickComponentHDLGeneratorFactory.FPGAClock + ";");
        }
    }
    /* Here we define all wiring; hence all complex splitter connections */
    ArrayList<String> Wiring = GetHDLWiring(HDLType, TheNetlist);
    if (!Wiring.isEmpty()) {
        Contents.add("");
        Contents.addAll(MakeRemarkBlock("Here all wiring is defined", 3, HDLType));
        Contents.addAll(Wiring);
    }
    /* Now we define all input signals; hence Input port -> Internal Net */
    FirstLine = true;
    for (int i = 0; i < TheNetlist.NumberOfInputPorts(); i++) {
        if (FirstLine) {
            Contents.add("");
            Contents.addAll(MakeRemarkBlock("Here all input connections are defined", 3, HDLType));
            FirstLine = false;
        }
        NetlistComponent MyInput = TheNetlist.GetInputPin(i);
        if (!(MyInput.GetComponent().getFactory() instanceof ReptarLocalBus)) {
            Contents.add(GetSignalMap(CorrectLabel.getCorrectLabel(MyInput.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)), MyInput, 0, 3, Reporter, HDLType, TheNetlist));
        }
    }
    // /* Now we define all inout signals; hence InOut port -> Internal Net
    // */
    // FirstLine = true;
    // for (int i = 0; i < TheNetlist.NumberOfInOutPorts(); i++) {
    // if (FirstLine) {
    // Contents.add("");
    // Contents.addAll(MakeRemarkBlock("Here all inout connections are defined",
    // 3, HDLType));
    // FirstLine = false;
    // }
    // NetlistComponent MyInOut = TheNetlist.GetInOutPin(i);
    // Contents.add(GetSignalMap(CorrectLabel.getCorrectLabel(MyInOut.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)),
    // MyInOut, 0, 3, Reporter, HDLType, TheNetlist));
    // }
    /* Now we define all output signals; hence Internal Net -> Input port */
    FirstLine = true;
    for (int i = 0; i < TheNetlist.NumberOfOutputPorts(); i++) {
        if (FirstLine) {
            Contents.add("");
            Contents.addAll(MakeRemarkBlock("Here all output connections are defined", 3, HDLType));
            FirstLine = false;
        }
        NetlistComponent MyOutput = TheNetlist.GetOutputPin(i);
        if (!(MyOutput.GetComponent().getFactory() instanceof ReptarLocalBus)) {
            Contents.add(GetSignalMap(CorrectLabel.getCorrectLabel(MyOutput.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)), MyOutput, 0, 3, Reporter, HDLType, TheNetlist));
        }
    }
    /* Here all in-lined components are generated */
    FirstLine = true;
    for (NetlistComponent comp : TheNetlist.GetNormalComponents()) {
        HDLGeneratorFactory Worker = comp.GetComponent().getFactory().getHDLGenerator(HDLType, comp.GetComponent().getAttributeSet());
        if (Worker != null) {
            if (Worker.IsOnlyInlined(HDLType)) {
                String InlinedName = comp.GetComponent().getFactory().getHDLName(comp.GetComponent().getAttributeSet());
                String InlinedId = Worker.getComponentStringIdentifier();
                Long id;
                if (CompIds.containsKey(InlinedId)) {
                    id = CompIds.get(InlinedId);
                } else {
                    id = (long) 1;
                }
                if (FirstLine) {
                    Contents.add("");
                    Contents.addAll(MakeRemarkBlock("Here all in-lined components are defined", 3, HDLType));
                    FirstLine = false;
                }
                Contents.addAll(Worker.GetInlinedCode(TheNetlist, id++, comp, Reporter, InlinedName, HDLType));
                if (CompIds.containsKey(InlinedId)) {
                    CompIds.remove(InlinedId);
                }
                CompIds.put(InlinedId, id);
            }
        }
    }
    /* Here all "normal" components are generated */
    FirstLine = true;
    for (NetlistComponent comp : TheNetlist.GetNormalComponents()) {
        HDLGeneratorFactory Worker = comp.GetComponent().getFactory().getHDLGenerator(HDLType, comp.GetComponent().getAttributeSet());
        if (Worker != null) {
            if (!Worker.IsOnlyInlined(HDLType)) {
                String CompName = comp.GetComponent().getFactory().getHDLName(comp.GetComponent().getAttributeSet());
                String CompId = Worker.getComponentStringIdentifier();
                Long id;
                if (CompIds.containsKey(CompId)) {
                    id = CompIds.get(CompId);
                } else {
                    id = (long) 1;
                }
                if (FirstLine) {
                    Contents.add("");
                    Contents.addAll(MakeRemarkBlock("Here all normal components are defined", 3, HDLType));
                    FirstLine = false;
                }
                Contents.addAll(Worker.GetComponentMap(TheNetlist, id++, comp, Reporter, CompName, HDLType));
                if (CompIds.containsKey(CompId)) {
                    CompIds.remove(CompId);
                }
                CompIds.put(CompId, id);
            }
        }
    }
    /* Finally we instantiate all sub-circuits */
    FirstLine = true;
    for (NetlistComponent comp : TheNetlist.GetSubCircuits()) {
        HDLGeneratorFactory Worker = comp.GetComponent().getFactory().getHDLGenerator(HDLType, comp.GetComponent().getAttributeSet());
        if (Worker != null) {
            String CompName = comp.GetComponent().getFactory().getHDLName(comp.GetComponent().getAttributeSet());
            String CompId = Worker.getComponentStringIdentifier();
            Long id;
            if (CompIds.containsKey(CompId)) {
                id = CompIds.get(CompId);
            } else {
                id = (long) 1;
            }
            ArrayList<String> CompMap = Worker.GetComponentMap(TheNetlist, id++, comp, Reporter, CompName, HDLType);
            if (!CompMap.isEmpty()) {
                if (FirstLine) {
                    Contents.add("");
                    Contents.addAll(MakeRemarkBlock("Here all sub-circuits are defined", 3, HDLType));
                    FirstLine = false;
                }
                if (CompIds.containsKey(CompId)) {
                    CompIds.remove(CompId);
                }
                CompIds.put(CompId, id);
                Contents.addAll(CompMap);
            }
        }
    }
    Contents.add("");
    return Contents;
}

Example 8 with NetlistComponent

use of com.bfh.logisim.designrulecheck.NetlistComponent in project logisim-evolution by reds-heig.

the class CircuitHDLGeneratorFactory method GetOutputList.

@Override
public SortedMap<String, Integer> GetOutputList(Netlist MyNetList, AttributeSet attrs) {
    SortedMap<String, Integer> Outputs = new TreeMap<String, Integer>();
    int OutputBubbles = MyNetList.NumberOfOutputBubbles();
    if (OutputBubbles > 0) {
        if (OutputBubbles > 1) {
            Outputs.put(HDLGeneratorFactory.LocalOutputBubbleBusname, OutputBubbles);
        } else {
            Outputs.put(HDLGeneratorFactory.LocalOutputBubbleBusname, 0);
        }
    }
    for (int i = 0; i < MyNetList.NumberOfOutputPorts(); i++) {
        NetlistComponent selected = MyNetList.GetOutputPin(i);
        if (selected != null) {
            if (!(selected.GetComponent().getFactory() instanceof ReptarLocalBus)) {
                Outputs.put(CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)), selected.GetComponent().getAttributeSet().getValue(StdAttr.WIDTH).getWidth());
            } else {
                Outputs.put(CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "_o"), selected.GetIOInformationContainer().GetNrOfOutports());
            }
        }
    }
    return Outputs;
}

Example 9 with NetlistComponent

use of com.bfh.logisim.designrulecheck.NetlistComponent in project logisim-evolution by reds-heig.

the class CircuitHDLGeneratorFactory method GetComponentDeclarationSection.

@Override
public ArrayList<String> GetComponentDeclarationSection(Netlist TheNetlist, AttributeSet attrs) {
    ArrayList<String> Components = new ArrayList<String>();
    Set<String> InstantiatedComponents = new HashSet<String>();
    for (NetlistComponent Gate : TheNetlist.GetNormalComponents()) {
        String CompName = Gate.GetComponent().getFactory().getHDLName(Gate.GetComponent().getAttributeSet());
        if (!InstantiatedComponents.contains(CompName)) {
            InstantiatedComponents.add(CompName);
            HDLGeneratorFactory Worker = Gate.GetComponent().getFactory().getHDLGenerator(VHDL, Gate.GetComponent().getAttributeSet());
            if (Worker != null) {
                if (!Worker.IsOnlyInlined(VHDL)) {
                    Components.addAll(Worker.GetComponentInstantiation(TheNetlist, Gate.GetComponent().getAttributeSet(), CompName, VHDL));
                }
            }
        }
    }
    InstantiatedComponents.clear();
    for (NetlistComponent Gate : TheNetlist.GetSubCircuits()) {
        String CompName = Gate.GetComponent().getFactory().getHDLName(Gate.GetComponent().getAttributeSet());
        if (!InstantiatedComponents.contains(CompName)) {
            InstantiatedComponents.add(CompName);
            HDLGeneratorFactory Worker = Gate.GetComponent().getFactory().getHDLGenerator(VHDL, Gate.GetComponent().getAttributeSet());
            SubcircuitFactory sub = (SubcircuitFactory) Gate.GetComponent().getFactory();
            if (Worker != null) {
                Components.addAll(Worker.GetComponentInstantiation(sub.getSubcircuit().getNetList(), Gate.GetComponent().getAttributeSet(), CompName, VHDL));
            }
        }
    }
    return Components;
}

Example 10 with NetlistComponent

use of com.bfh.logisim.designrulecheck.NetlistComponent in project logisim-evolution by reds-heig.

the class CircuitHDLGeneratorFactory method GetInputList.

@Override
public SortedMap<String, Integer> GetInputList(Netlist MyNetList, AttributeSet attrs) {
    SortedMap<String, Integer> Inputs = new TreeMap<String, Integer>();
    for (int i = 0; i < MyNetList.NumberOfClockTrees(); i++) {
        Inputs.put(ClockTreeName + Integer.toString(i), ClockHDLGeneratorFactory.NrOfClockBits);
    }
    if (MyNetList.RequiresGlobalClockConnection()) {
        Inputs.put(TickComponentHDLGeneratorFactory.FPGAClock, 1);
    }
    int InputBubbles = MyNetList.NumberOfInputBubbles();
    if (InputBubbles > 0) {
        if (InputBubbles > 1) {
            Inputs.put(HDLGeneratorFactory.LocalInputBubbleBusname, InputBubbles);
        } else {
            Inputs.put(HDLGeneratorFactory.LocalInputBubbleBusname, 0);
        }
    }
    for (int i = 0; i < MyNetList.NumberOfInputPorts(); i++) {
        NetlistComponent selected = MyNetList.GetInputPin(i);
        if (selected != null) {
            if (!(selected.GetComponent().getFactory() instanceof ReptarLocalBus)) {
                Inputs.put(CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL)), selected.GetComponent().getAttributeSet().getValue(StdAttr.WIDTH).getWidth());
            } else {
                Inputs.put(CorrectLabel.getCorrectLabel(selected.GetComponent().getAttributeSet().getValue(StdAttr.LABEL) + "_i"), selected.GetIOInformationContainer().GetNrOfInports());
            }
        }
    }
    return Inputs;
}