use of com.cburch.logisim.std.io.ReptarLocalBus in project logisim-evolution by reds-heig.
the class ToplevelHDLGeneratorFactory method GetModuleFunctionality.
@Override
public ArrayList<String> GetModuleFunctionality(Netlist TheNetlist, AttributeSet attrs, FPGAReport Reporter, String HDLType) {
ArrayList<String> Contents = new ArrayList<String>();
int NrOfClockTrees = TheNetlist.NumberOfClockTrees();
String Preamble = (HDLType.equals(VHDL)) ? "" : "assign ";
String BracketOpen = (HDLType.equals(VHDL)) ? "(" : "[";
String BracketClose = (HDLType.equals(VHDL)) ? ")" : "]";
String AssignOperator = (HDLType.equals(VHDL)) ? " <= " : " = ";
String NotOperator = (HDLType.equals(VHDL)) ? "NOT " : "~";
StringBuffer Temp = new StringBuffer();
/* First we process all pins */
Contents.addAll(MakeRemarkBlock("Here all signal adaptations are performed", 3, HDLType));
for (ArrayList<String> CompId : MyIOComponents.GetComponents()) {
if (MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof Pin) {
Component ThisPin = MyIOComponents.GetComponent(CompId).GetComponent();
ArrayList<String> MyMaps = MyIOComponents.GetMapNamesList(CompId);
if (MyMaps == null) {
Reporter.AddFatalError("Component has no map information, bizar! " + CompId.toString());
return Contents;
}
int PinPinId = 0;
for (int MapOffset = 0; MapOffset < MyMaps.size(); MapOffset++) {
String map = MyMaps.get(MapOffset);
int InputId = MyIOComponents.GetFPGAInputPinId(map);
int OutputId = MyIOComponents.GetFPGAOutputPinId(map);
int NrOfPins = MyIOComponents.GetNrOfPins(map);
boolean Invert = MyIOComponents.RequiresToplevelInversion(CompId, map);
for (int PinId = 0; PinId < NrOfPins; PinId++) {
Temp.setLength(0);
Temp.append(" " + Preamble);
if (InputId >= 0) {
Temp.append("s_" + CorrectLabel.getCorrectLabel(ThisPin.getAttributeSet().getValue(StdAttr.LABEL)));
if (ThisPin.getEnd(0).getWidth().getWidth() > 1) {
Temp.append(BracketOpen + PinPinId + BracketClose);
}
PinPinId++;
Temp.append(AssignOperator);
if (Invert) {
Temp.append(NotOperator);
}
Temp.append(HDLGeneratorFactory.FPGAInputPinName);
Temp.append("_" + Integer.toString(InputId + PinId));
Temp.append(";");
Contents.add(Temp.toString());
}
if (OutputId >= 0) {
Temp.append(HDLGeneratorFactory.FPGAOutputPinName);
Temp.append("_" + Integer.toString(OutputId + PinId));
Temp.append(AssignOperator);
if (Invert) {
Temp.append(NotOperator);
}
Temp.append("s_" + CorrectLabel.getCorrectLabel(ThisPin.getAttributeSet().getValue(StdAttr.LABEL)));
if (ThisPin.getEnd(0).getWidth().getWidth() > 1) {
Temp.append(BracketOpen + PinPinId + BracketClose);
}
PinPinId++;
Temp.append(";");
Contents.add(Temp.toString());
}
}
}
}
}
/* Now we process the bubbles */
Contents.addAll(MakeRemarkBlock("Here all inlined adaptations are performed", 3, HDLType));
for (ArrayList<String> CompId : MyIOComponents.GetComponents()) {
if (!(MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof Pin) && !(MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof PortIO) && !(MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof ReptarLocalBus)) {
HDLGeneratorFactory Generator = MyIOComponents.GetComponent(CompId).GetComponent().getFactory().getHDLGenerator(HDLType, MyIOComponents.GetComponent(CompId).GetComponent().getAttributeSet());
if (Generator == null) {
Reporter.AddError("No generator for component " + CompId.toString());
} else {
Contents.addAll(Generator.GetInlinedCode(HDLType, CompId, Reporter, MyIOComponents));
}
} else if (MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof ReptarLocalBus) {
((ReptarLocalBus) MyIOComponents.GetComponent(CompId).GetComponent().getFactory()).setMapInfo(MyIOComponents);
} else if (MyIOComponents.GetComponent(CompId).GetComponent().getFactory() instanceof PortIO) {
((PortIO) MyIOComponents.GetComponent(CompId).GetComponent().getFactory()).setMapInfo(MyIOComponents);
}
}
if (NrOfClockTrees > 0) {
Contents.addAll(MakeRemarkBlock("Here the clock tree components are defined", 3, HDLType));
TickComponentHDLGeneratorFactory Ticker = new TickComponentHDLGeneratorFactory(FpgaClockFrequency, TickFrequency);
Contents.addAll(Ticker.GetComponentMap(null, (long) 0, null, Reporter, "", HDLType));
long index = 0;
for (Component Clockgen : TheNetlist.GetAllClockSources()) {
NetlistComponent ThisClock = new NetlistComponent(Clockgen);
Contents.addAll(Clockgen.getFactory().getHDLGenerator(HDLType, ThisClock.GetComponent().getAttributeSet()).GetComponentMap(TheNetlist, index++, ThisClock, Reporter, "Bla", HDLType));
}
}
Contents.add("");
/* Here the map is performed */
Contents.addAll(MakeRemarkBlock("Here the toplevel component is connected", 3, HDLType));
CircuitHDLGeneratorFactory DUT = new CircuitHDLGeneratorFactory(MyCircuit);
Contents.addAll(DUT.GetComponentMap(TheNetlist, (long) 0, null, Reporter, CorrectLabel.getCorrectLabel(MyCircuit.getName()), HDLType));
return Contents;
}
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